402 lines
10 KiB
C
402 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (C) STMicroelectronics SA 2017
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* Author(s): M'boumba Cedric Madianga <cedric.madianga@gmail.com>
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* Pierre-Yves Mordret <pierre-yves.mordret@st.com>
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*
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* DMA Router driver for STM32 DMA MUX
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*
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* Based on TI DMA Crossbar driver
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#define STM32_DMAMUX_CCR(x) (0x4 * (x))
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#define STM32_DMAMUX_MAX_DMA_REQUESTS 32
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#define STM32_DMAMUX_MAX_REQUESTS 255
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struct stm32_dmamux {
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u32 master;
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u32 request;
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u32 chan_id;
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};
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struct stm32_dmamux_data {
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struct dma_router dmarouter;
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struct clk *clk;
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void __iomem *iomem;
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u32 dma_requests; /* Number of DMA requests connected to DMAMUX */
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u32 dmamux_requests; /* Number of DMA requests routed toward DMAs */
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spinlock_t lock; /* Protects register access */
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DECLARE_BITMAP(dma_inuse, STM32_DMAMUX_MAX_DMA_REQUESTS); /* Used DMA channel */
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u32 ccr[STM32_DMAMUX_MAX_DMA_REQUESTS]; /* Used to backup CCR register
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* in suspend
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*/
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u32 dma_reqs[]; /* Number of DMA Request per DMA masters.
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* [0] holds number of DMA Masters.
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* To be kept at very end of this structure
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*/
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};
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static inline u32 stm32_dmamux_read(void __iomem *iomem, u32 reg)
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{
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return readl_relaxed(iomem + reg);
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}
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static inline void stm32_dmamux_write(void __iomem *iomem, u32 reg, u32 val)
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{
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writel_relaxed(val, iomem + reg);
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}
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static void stm32_dmamux_free(struct device *dev, void *route_data)
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{
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struct stm32_dmamux_data *dmamux = dev_get_drvdata(dev);
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struct stm32_dmamux *mux = route_data;
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unsigned long flags;
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/* Clear dma request */
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spin_lock_irqsave(&dmamux->lock, flags);
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stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id), 0);
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clear_bit(mux->chan_id, dmamux->dma_inuse);
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pm_runtime_put_sync(dev);
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spin_unlock_irqrestore(&dmamux->lock, flags);
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dev_dbg(dev, "Unmapping DMAMUX(%u) to DMA%u(%u)\n",
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mux->request, mux->master, mux->chan_id);
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kfree(mux);
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}
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static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,
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struct of_dma *ofdma)
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{
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struct platform_device *pdev = of_find_device_by_node(ofdma->of_node);
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struct stm32_dmamux_data *dmamux = platform_get_drvdata(pdev);
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struct stm32_dmamux *mux;
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u32 i, min, max;
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int ret;
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unsigned long flags;
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if (dma_spec->args_count != 3) {
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dev_err(&pdev->dev, "invalid number of dma mux args\n");
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return ERR_PTR(-EINVAL);
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}
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if (dma_spec->args[0] > dmamux->dmamux_requests) {
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dev_err(&pdev->dev, "invalid mux request number: %d\n",
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dma_spec->args[0]);
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return ERR_PTR(-EINVAL);
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}
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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spin_lock_irqsave(&dmamux->lock, flags);
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mux->chan_id = find_first_zero_bit(dmamux->dma_inuse,
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dmamux->dma_requests);
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if (mux->chan_id == dmamux->dma_requests) {
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spin_unlock_irqrestore(&dmamux->lock, flags);
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dev_err(&pdev->dev, "Run out of free DMA requests\n");
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ret = -ENOMEM;
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goto error_chan_id;
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}
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set_bit(mux->chan_id, dmamux->dma_inuse);
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spin_unlock_irqrestore(&dmamux->lock, flags);
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/* Look for DMA Master */
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for (i = 1, min = 0, max = dmamux->dma_reqs[i];
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i <= dmamux->dma_reqs[0];
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min += dmamux->dma_reqs[i], max += dmamux->dma_reqs[++i])
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if (mux->chan_id < max)
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break;
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mux->master = i - 1;
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/* The of_node_put() will be done in of_dma_router_xlate function */
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dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", i - 1);
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if (!dma_spec->np) {
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dev_err(&pdev->dev, "can't get dma master\n");
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ret = -EINVAL;
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goto error;
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}
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/* Set dma request */
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spin_lock_irqsave(&dmamux->lock, flags);
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ret = pm_runtime_resume_and_get(&pdev->dev);
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if (ret < 0) {
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spin_unlock_irqrestore(&dmamux->lock, flags);
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goto error;
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}
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spin_unlock_irqrestore(&dmamux->lock, flags);
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mux->request = dma_spec->args[0];
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/* craft DMA spec */
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dma_spec->args[3] = dma_spec->args[2] | mux->chan_id << 16;
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dma_spec->args[2] = dma_spec->args[1];
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dma_spec->args[1] = 0;
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dma_spec->args[0] = mux->chan_id - min;
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dma_spec->args_count = 4;
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stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id),
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mux->request);
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dev_dbg(&pdev->dev, "Mapping DMAMUX(%u) to DMA%u(%u)\n",
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mux->request, mux->master, mux->chan_id);
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return mux;
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error:
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clear_bit(mux->chan_id, dmamux->dma_inuse);
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error_chan_id:
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kfree(mux);
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return ERR_PTR(ret);
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}
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static const struct of_device_id stm32_stm32dma_master_match[] __maybe_unused = {
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{ .compatible = "st,stm32-dma", },
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{},
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};
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static int stm32_dmamux_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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const struct of_device_id *match;
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struct device_node *dma_node;
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struct stm32_dmamux_data *stm32_dmamux;
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void __iomem *iomem;
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struct reset_control *rst;
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int i, count, ret;
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u32 dma_req;
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if (!node)
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return -ENODEV;
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count = device_property_count_u32(&pdev->dev, "dma-masters");
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if (count < 0) {
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dev_err(&pdev->dev, "Can't get DMA master(s) node\n");
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return -ENODEV;
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}
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stm32_dmamux = devm_kzalloc(&pdev->dev, sizeof(*stm32_dmamux) +
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sizeof(u32) * (count + 1), GFP_KERNEL);
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if (!stm32_dmamux)
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return -ENOMEM;
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dma_req = 0;
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for (i = 1; i <= count; i++) {
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dma_node = of_parse_phandle(node, "dma-masters", i - 1);
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match = of_match_node(stm32_stm32dma_master_match, dma_node);
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if (!match) {
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dev_err(&pdev->dev, "DMA master is not supported\n");
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of_node_put(dma_node);
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return -EINVAL;
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}
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if (of_property_read_u32(dma_node, "dma-requests",
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&stm32_dmamux->dma_reqs[i])) {
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dev_info(&pdev->dev,
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"Missing MUX output information, using %u.\n",
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STM32_DMAMUX_MAX_DMA_REQUESTS);
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stm32_dmamux->dma_reqs[i] =
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STM32_DMAMUX_MAX_DMA_REQUESTS;
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}
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dma_req += stm32_dmamux->dma_reqs[i];
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of_node_put(dma_node);
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}
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if (dma_req > STM32_DMAMUX_MAX_DMA_REQUESTS) {
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dev_err(&pdev->dev, "Too many DMA Master Requests to manage\n");
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return -ENODEV;
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}
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stm32_dmamux->dma_requests = dma_req;
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stm32_dmamux->dma_reqs[0] = count;
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if (device_property_read_u32(&pdev->dev, "dma-requests",
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&stm32_dmamux->dmamux_requests)) {
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stm32_dmamux->dmamux_requests = STM32_DMAMUX_MAX_REQUESTS;
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dev_warn(&pdev->dev, "DMAMUX defaulting on %u requests\n",
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stm32_dmamux->dmamux_requests);
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}
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pm_runtime_get_noresume(&pdev->dev);
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iomem = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(iomem))
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return PTR_ERR(iomem);
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spin_lock_init(&stm32_dmamux->lock);
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stm32_dmamux->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(stm32_dmamux->clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(stm32_dmamux->clk),
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"Missing clock controller\n");
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ret = clk_prepare_enable(stm32_dmamux->clk);
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if (ret < 0) {
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dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
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return ret;
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}
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rst = devm_reset_control_get(&pdev->dev, NULL);
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if (IS_ERR(rst)) {
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ret = PTR_ERR(rst);
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if (ret == -EPROBE_DEFER)
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goto err_clk;
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} else if (count > 1) { /* Don't reset if there is only one dma-master */
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reset_control_assert(rst);
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udelay(2);
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reset_control_deassert(rst);
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}
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stm32_dmamux->iomem = iomem;
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stm32_dmamux->dmarouter.dev = &pdev->dev;
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stm32_dmamux->dmarouter.route_free = stm32_dmamux_free;
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platform_set_drvdata(pdev, stm32_dmamux);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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pm_runtime_get_noresume(&pdev->dev);
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/* Reset the dmamux */
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for (i = 0; i < stm32_dmamux->dma_requests; i++)
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stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i), 0);
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pm_runtime_put(&pdev->dev);
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ret = of_dma_router_register(node, stm32_dmamux_route_allocate,
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&stm32_dmamux->dmarouter);
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if (ret)
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goto pm_disable;
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return 0;
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pm_disable:
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pm_runtime_disable(&pdev->dev);
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err_clk:
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clk_disable_unprepare(stm32_dmamux->clk);
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return ret;
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}
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#ifdef CONFIG_PM
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static int stm32_dmamux_runtime_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
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clk_disable_unprepare(stm32_dmamux->clk);
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return 0;
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}
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static int stm32_dmamux_runtime_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
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int ret;
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ret = clk_prepare_enable(stm32_dmamux->clk);
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if (ret) {
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dev_err(&pdev->dev, "failed to prepare_enable clock\n");
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return ret;
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}
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return 0;
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}
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#endif
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#ifdef CONFIG_PM_SLEEP
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static int stm32_dmamux_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
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int i, ret;
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ret = pm_runtime_resume_and_get(dev);
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if (ret < 0)
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return ret;
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for (i = 0; i < stm32_dmamux->dma_requests; i++)
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stm32_dmamux->ccr[i] = stm32_dmamux_read(stm32_dmamux->iomem,
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STM32_DMAMUX_CCR(i));
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pm_runtime_put_sync(dev);
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pm_runtime_force_suspend(dev);
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return 0;
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}
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static int stm32_dmamux_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
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int i, ret;
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ret = pm_runtime_force_resume(dev);
|
||
|
|
if (ret < 0)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
ret = pm_runtime_resume_and_get(dev);
|
||
|
|
if (ret < 0)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
for (i = 0; i < stm32_dmamux->dma_requests; i++)
|
||
|
|
stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i),
|
||
|
|
stm32_dmamux->ccr[i]);
|
||
|
|
|
||
|
|
pm_runtime_put_sync(dev);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static const struct dev_pm_ops stm32_dmamux_pm_ops = {
|
||
|
|
SET_SYSTEM_SLEEP_PM_OPS(stm32_dmamux_suspend, stm32_dmamux_resume)
|
||
|
|
SET_RUNTIME_PM_OPS(stm32_dmamux_runtime_suspend,
|
||
|
|
stm32_dmamux_runtime_resume, NULL)
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id stm32_dmamux_match[] = {
|
||
|
|
{ .compatible = "st,stm32h7-dmamux" },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_driver stm32_dmamux_driver = {
|
||
|
|
.probe = stm32_dmamux_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "stm32-dmamux",
|
||
|
|
.of_match_table = stm32_dmamux_match,
|
||
|
|
.pm = &stm32_dmamux_pm_ops,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init stm32_dmamux_init(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&stm32_dmamux_driver);
|
||
|
|
}
|
||
|
|
arch_initcall(stm32_dmamux_init);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("DMA Router driver for STM32 DMA MUX");
|
||
|
|
MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
|
||
|
|
MODULE_AUTHOR("Pierre-Yves Mordret <pierre-yves.mordret@st.com>");
|
||
|
|
MODULE_LICENSE("GPL v2");
|