527 lines
17 KiB
C
527 lines
17 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Huang Rui
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*
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*/
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#ifndef __AMDGPU_PSP_H__
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#define __AMDGPU_PSP_H__
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#include "amdgpu.h"
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#include "psp_gfx_if.h"
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#include "ta_xgmi_if.h"
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#include "ta_ras_if.h"
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#include "ta_rap_if.h"
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#include "ta_secureDisplay_if.h"
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#define PSP_FENCE_BUFFER_SIZE 0x1000
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#define PSP_CMD_BUFFER_SIZE 0x1000
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#define PSP_1_MEG 0x100000
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#define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
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#define PSP_TMR_ALIGNMENT 0x100000
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#define PSP_FW_NAME_LEN 0x24
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enum psp_shared_mem_size {
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PSP_ASD_SHARED_MEM_SIZE = 0x0,
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PSP_XGMI_SHARED_MEM_SIZE = 0x4000,
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PSP_RAS_SHARED_MEM_SIZE = 0x4000,
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PSP_HDCP_SHARED_MEM_SIZE = 0x4000,
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PSP_DTM_SHARED_MEM_SIZE = 0x4000,
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PSP_RAP_SHARED_MEM_SIZE = 0x4000,
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PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000,
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};
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enum ta_type_id {
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TA_TYPE_XGMI = 1,
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TA_TYPE_RAS,
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TA_TYPE_HDCP,
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TA_TYPE_DTM,
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TA_TYPE_RAP,
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TA_TYPE_SECUREDISPLAY,
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TA_TYPE_MAX_INDEX,
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};
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struct psp_context;
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struct psp_xgmi_node_info;
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struct psp_xgmi_topology_info;
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struct psp_bin_desc;
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enum psp_bootloader_cmd {
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PSP_BL__LOAD_SYSDRV = 0x10000,
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PSP_BL__LOAD_SOSDRV = 0x20000,
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PSP_BL__LOAD_KEY_DATABASE = 0x80000,
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PSP_BL__LOAD_SOCDRV = 0xB0000,
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PSP_BL__LOAD_DBGDRV = 0xC0000,
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PSP_BL__LOAD_INTFDRV = 0xD0000,
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PSP_BL__LOAD_RASDRV = 0xE0000,
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PSP_BL__DRAM_LONG_TRAIN = 0x100000,
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PSP_BL__DRAM_SHORT_TRAIN = 0x200000,
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PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000,
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};
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enum psp_ring_type
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{
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PSP_RING_TYPE__INVALID = 0,
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/*
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* These values map to the way the PSP kernel identifies the
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* rings.
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*/
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PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
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PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
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};
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struct psp_ring
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{
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enum psp_ring_type ring_type;
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struct psp_gfx_rb_frame *ring_mem;
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uint64_t ring_mem_mc_addr;
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void *ring_mem_handle;
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uint32_t ring_size;
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uint32_t ring_wptr;
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};
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/* More registers may will be supported */
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enum psp_reg_prog_id {
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PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */
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PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */
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PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */
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PSP_REG_LAST
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};
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struct psp_funcs
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{
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int (*init_microcode)(struct psp_context *psp);
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int (*bootloader_load_kdb)(struct psp_context *psp);
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int (*bootloader_load_spl)(struct psp_context *psp);
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int (*bootloader_load_sysdrv)(struct psp_context *psp);
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int (*bootloader_load_soc_drv)(struct psp_context *psp);
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int (*bootloader_load_intf_drv)(struct psp_context *psp);
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int (*bootloader_load_dbg_drv)(struct psp_context *psp);
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int (*bootloader_load_ras_drv)(struct psp_context *psp);
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int (*bootloader_load_sos)(struct psp_context *psp);
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int (*ring_create)(struct psp_context *psp,
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enum psp_ring_type ring_type);
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int (*ring_stop)(struct psp_context *psp,
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enum psp_ring_type ring_type);
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int (*ring_destroy)(struct psp_context *psp,
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enum psp_ring_type ring_type);
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bool (*smu_reload_quirk)(struct psp_context *psp);
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int (*mode1_reset)(struct psp_context *psp);
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int (*mem_training)(struct psp_context *psp, uint32_t ops);
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uint32_t (*ring_get_wptr)(struct psp_context *psp);
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void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
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int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
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int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
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int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
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int (*vbflash_stat)(struct psp_context *psp);
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};
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struct ta_funcs {
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int (*fn_ta_initialize)(struct psp_context *psp);
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int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id);
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int (*fn_ta_terminate)(struct psp_context *psp);
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};
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#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
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struct psp_xgmi_node_info {
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uint64_t node_id;
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uint8_t num_hops;
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uint8_t is_sharing_enabled;
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enum ta_xgmi_assigned_sdma_engine sdma_engine;
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uint8_t num_links;
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};
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struct psp_xgmi_topology_info {
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uint32_t num_nodes;
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struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
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};
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struct psp_bin_desc {
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uint32_t fw_version;
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uint32_t feature_version;
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uint32_t size_bytes;
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uint8_t *start_addr;
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};
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struct ta_mem_context {
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struct amdgpu_bo *shared_bo;
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uint64_t shared_mc_addr;
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void *shared_buf;
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enum psp_shared_mem_size shared_mem_size;
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};
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struct ta_context {
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bool initialized;
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uint32_t session_id;
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uint32_t resp_status;
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struct ta_mem_context mem_context;
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struct psp_bin_desc bin_desc;
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enum psp_gfx_cmd_id ta_load_type;
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enum ta_type_id ta_type;
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};
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struct ta_cp_context {
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struct ta_context context;
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struct mutex mutex;
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};
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struct psp_xgmi_context {
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struct ta_context context;
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struct psp_xgmi_topology_info top_info;
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bool supports_extended_data;
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};
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struct psp_ras_context {
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struct ta_context context;
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struct amdgpu_ras *ras;
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};
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#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942
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#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000
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#define GDDR6_MEM_TRAINING_OFFSET 0x8000
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/*Define the VRAM size that will be encroached by BIST training.*/
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#define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000
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enum psp_memory_training_init_flag {
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PSP_MEM_TRAIN_NOT_SUPPORT = 0x0,
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PSP_MEM_TRAIN_SUPPORT = 0x1,
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PSP_MEM_TRAIN_INIT_FAILED = 0x2,
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PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4,
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PSP_MEM_TRAIN_INIT_SUCCESS = 0x8,
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};
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enum psp_memory_training_ops {
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PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1,
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PSP_MEM_TRAIN_SAVE = 0x2,
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PSP_MEM_TRAIN_RESTORE = 0x4,
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PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8,
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PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG,
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PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG,
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};
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struct psp_memory_training_context {
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/*training data size*/
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u64 train_data_size;
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/*
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* sys_cache
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* cpu virtual address
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* system memory buffer that used to store the training data.
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*/
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void *sys_cache;
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/*vram offset of the p2c training data*/
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u64 p2c_train_data_offset;
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/*vram offset of the c2p training data*/
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u64 c2p_train_data_offset;
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struct amdgpu_bo *c2p_bo;
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enum psp_memory_training_init_flag init;
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u32 training_cnt;
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bool enable_mem_training;
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};
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/** PSP runtime DB **/
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#define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000
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#define PSP_RUNTIME_DB_OFFSET 0x100000
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#define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5
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#define PSP_RUNTIME_DB_VER_1 0x0100
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#define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40
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enum psp_runtime_entry_type {
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PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0,
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PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1,
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PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */
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PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */
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PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */
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PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */
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PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */
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};
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/* PSP runtime DB header */
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struct psp_runtime_data_header {
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/* determine the existence of runtime db */
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uint16_t cookie;
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/* version of runtime db */
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uint16_t version;
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};
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/* PSP runtime DB entry */
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struct psp_runtime_entry {
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/* type of runtime db entry */
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uint32_t entry_type;
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/* offset of entry in bytes */
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uint16_t offset;
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/* size of entry in bytes */
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uint16_t size;
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};
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/* PSP runtime DB directory */
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struct psp_runtime_data_directory {
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/* number of valid entries */
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uint16_t entry_count;
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/* db entries*/
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struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
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};
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/* PSP runtime DB boot config feature bitmask */
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enum psp_runtime_boot_cfg_feature {
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BOOT_CFG_FEATURE_GECC = 0x1,
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BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2,
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};
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/* PSP run time DB SCPM authentication defines */
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enum psp_runtime_scpm_authentication {
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SCPM_DISABLE = 0x0,
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SCPM_ENABLE = 0x1,
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SCPM_ENABLE_WITH_SCPM_ERR = 0x2,
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};
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/* PSP runtime DB boot config entry */
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struct psp_runtime_boot_cfg_entry {
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uint32_t boot_cfg_bitmask;
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uint32_t reserved;
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};
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/* PSP runtime DB SCPM entry */
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struct psp_runtime_scpm_entry {
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enum psp_runtime_scpm_authentication scpm_status;
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};
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struct psp_context
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{
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struct amdgpu_device *adev;
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struct psp_ring km_ring;
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struct psp_gfx_cmd_resp *cmd;
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const struct psp_funcs *funcs;
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const struct ta_funcs *ta_funcs;
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/* firmware buffer */
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struct amdgpu_bo *fw_pri_bo;
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uint64_t fw_pri_mc_addr;
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void *fw_pri_buf;
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/* sos firmware */
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const struct firmware *sos_fw;
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struct psp_bin_desc sys;
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struct psp_bin_desc sos;
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struct psp_bin_desc toc;
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struct psp_bin_desc kdb;
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struct psp_bin_desc spl;
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struct psp_bin_desc rl;
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struct psp_bin_desc soc_drv;
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struct psp_bin_desc intf_drv;
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struct psp_bin_desc dbg_drv;
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struct psp_bin_desc ras_drv;
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/* tmr buffer */
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struct amdgpu_bo *tmr_bo;
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uint64_t tmr_mc_addr;
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/* asd firmware */
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const struct firmware *asd_fw;
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/* toc firmware */
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const struct firmware *toc_fw;
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|
|
|
||
|
|
/* cap firmware */
|
||
|
|
const struct firmware *cap_fw;
|
||
|
|
|
||
|
|
/* fence buffer */
|
||
|
|
struct amdgpu_bo *fence_buf_bo;
|
||
|
|
uint64_t fence_buf_mc_addr;
|
||
|
|
void *fence_buf;
|
||
|
|
|
||
|
|
/* cmd buffer */
|
||
|
|
struct amdgpu_bo *cmd_buf_bo;
|
||
|
|
uint64_t cmd_buf_mc_addr;
|
||
|
|
struct psp_gfx_cmd_resp *cmd_buf_mem;
|
||
|
|
|
||
|
|
/* fence value associated with cmd buffer */
|
||
|
|
atomic_t fence_value;
|
||
|
|
/* flag to mark whether gfx fw autoload is supported or not */
|
||
|
|
bool autoload_supported;
|
||
|
|
/* flag to mark whether df cstate management centralized to PMFW */
|
||
|
|
bool pmfw_centralized_cstate_management;
|
||
|
|
|
||
|
|
/* xgmi ta firmware and buffer */
|
||
|
|
const struct firmware *ta_fw;
|
||
|
|
uint32_t ta_fw_version;
|
||
|
|
|
||
|
|
uint32_t cap_fw_version;
|
||
|
|
uint32_t cap_feature_version;
|
||
|
|
uint32_t cap_ucode_size;
|
||
|
|
|
||
|
|
struct ta_context asd_context;
|
||
|
|
struct psp_xgmi_context xgmi_context;
|
||
|
|
struct psp_ras_context ras_context;
|
||
|
|
struct ta_cp_context hdcp_context;
|
||
|
|
struct ta_cp_context dtm_context;
|
||
|
|
struct ta_cp_context rap_context;
|
||
|
|
struct ta_cp_context securedisplay_context;
|
||
|
|
struct mutex mutex;
|
||
|
|
struct psp_memory_training_context mem_train_ctx;
|
||
|
|
|
||
|
|
uint32_t boot_cfg_bitmask;
|
||
|
|
|
||
|
|
char *vbflash_tmp_buf;
|
||
|
|
size_t vbflash_image_size;
|
||
|
|
bool vbflash_done;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct amdgpu_psp_funcs {
|
||
|
|
bool (*check_fw_loading_status)(struct amdgpu_device *adev,
|
||
|
|
enum AMDGPU_UCODE_ID);
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
|
||
|
|
#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
|
||
|
|
#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
|
||
|
|
#define psp_init_microcode(psp) \
|
||
|
|
((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
|
||
|
|
#define psp_bootloader_load_kdb(psp) \
|
||
|
|
((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
|
||
|
|
#define psp_bootloader_load_spl(psp) \
|
||
|
|
((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
|
||
|
|
#define psp_bootloader_load_sysdrv(psp) \
|
||
|
|
((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
|
||
|
|
#define psp_bootloader_load_soc_drv(psp) \
|
||
|
|
((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
|
||
|
|
#define psp_bootloader_load_intf_drv(psp) \
|
||
|
|
((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
|
||
|
|
#define psp_bootloader_load_dbg_drv(psp) \
|
||
|
|
((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)
|
||
|
|
#define psp_bootloader_load_ras_drv(psp) \
|
||
|
|
((psp)->funcs->bootloader_load_ras_drv ? \
|
||
|
|
(psp)->funcs->bootloader_load_ras_drv((psp)) : 0)
|
||
|
|
#define psp_bootloader_load_sos(psp) \
|
||
|
|
((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
|
||
|
|
#define psp_smu_reload_quirk(psp) \
|
||
|
|
((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
|
||
|
|
#define psp_mode1_reset(psp) \
|
||
|
|
((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
|
||
|
|
#define psp_mem_training(psp, ops) \
|
||
|
|
((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
|
||
|
|
|
||
|
|
#define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
|
||
|
|
#define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
|
||
|
|
|
||
|
|
#define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \
|
||
|
|
((psp)->funcs->load_usbc_pd_fw ? \
|
||
|
|
(psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL)
|
||
|
|
|
||
|
|
#define psp_read_usbc_pd_fw(psp, fw_ver) \
|
||
|
|
((psp)->funcs->read_usbc_pd_fw ? \
|
||
|
|
(psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
|
||
|
|
|
||
|
|
#define psp_update_spirom(psp, fw_pri_mc_addr) \
|
||
|
|
((psp)->funcs->update_spirom ? \
|
||
|
|
(psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
|
||
|
|
|
||
|
|
#define psp_vbflash_status(psp) \
|
||
|
|
((psp)->funcs->vbflash_stat ? \
|
||
|
|
(psp)->funcs->vbflash_stat((psp)) : -EINVAL)
|
||
|
|
|
||
|
|
extern const struct amd_ip_funcs psp_ip_funcs;
|
||
|
|
|
||
|
|
extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
|
||
|
|
extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
|
||
|
|
extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
|
||
|
|
extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
|
||
|
|
extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
|
||
|
|
extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
|
||
|
|
extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
|
||
|
|
|
||
|
|
extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
|
||
|
|
uint32_t field_val, uint32_t mask, bool check_changed);
|
||
|
|
|
||
|
|
int psp_gpu_reset(struct amdgpu_device *adev);
|
||
|
|
int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
|
||
|
|
uint64_t cmd_gpu_addr, int cmd_size);
|
||
|
|
|
||
|
|
int psp_ta_init_shared_buf(struct psp_context *psp,
|
||
|
|
struct ta_mem_context *mem_ctx);
|
||
|
|
void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx);
|
||
|
|
int psp_ta_unload(struct psp_context *psp, struct ta_context *context);
|
||
|
|
int psp_ta_load(struct psp_context *psp, struct ta_context *context);
|
||
|
|
int psp_ta_invoke(struct psp_context *psp,
|
||
|
|
uint32_t ta_cmd_id,
|
||
|
|
struct ta_context *context);
|
||
|
|
|
||
|
|
int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta);
|
||
|
|
int psp_xgmi_terminate(struct psp_context *psp);
|
||
|
|
int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
|
||
|
|
int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
|
||
|
|
int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
|
||
|
|
int psp_xgmi_get_topology_info(struct psp_context *psp,
|
||
|
|
int number_devices,
|
||
|
|
struct psp_xgmi_topology_info *topology,
|
||
|
|
bool get_extended_data);
|
||
|
|
int psp_xgmi_set_topology_info(struct psp_context *psp,
|
||
|
|
int number_devices,
|
||
|
|
struct psp_xgmi_topology_info *topology);
|
||
|
|
int psp_ras_initialize(struct psp_context *psp);
|
||
|
|
int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
|
||
|
|
int psp_ras_enable_features(struct psp_context *psp,
|
||
|
|
union ta_ras_cmd_input *info, bool enable);
|
||
|
|
int psp_ras_trigger_error(struct psp_context *psp,
|
||
|
|
struct ta_ras_trigger_error_input *info);
|
||
|
|
int psp_ras_terminate(struct psp_context *psp);
|
||
|
|
|
||
|
|
int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
|
||
|
|
int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
|
||
|
|
int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
|
||
|
|
int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
|
||
|
|
|
||
|
|
int psp_rlc_autoload_start(struct psp_context *psp);
|
||
|
|
|
||
|
|
int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
|
||
|
|
uint32_t value);
|
||
|
|
int psp_ring_cmd_submit(struct psp_context *psp,
|
||
|
|
uint64_t cmd_buf_mc_addr,
|
||
|
|
uint64_t fence_mc_addr,
|
||
|
|
int index);
|
||
|
|
int psp_init_asd_microcode(struct psp_context *psp,
|
||
|
|
const char *chip_name);
|
||
|
|
int psp_init_toc_microcode(struct psp_context *psp,
|
||
|
|
const char *chip_name);
|
||
|
|
int psp_init_sos_microcode(struct psp_context *psp,
|
||
|
|
const char *chip_name);
|
||
|
|
int psp_init_ta_microcode(struct psp_context *psp,
|
||
|
|
const char *chip_name);
|
||
|
|
int psp_init_cap_microcode(struct psp_context *psp,
|
||
|
|
const char *chip_name);
|
||
|
|
int psp_get_fw_attestation_records_addr(struct psp_context *psp,
|
||
|
|
uint64_t *output_ptr);
|
||
|
|
|
||
|
|
int psp_load_fw_list(struct psp_context *psp,
|
||
|
|
struct amdgpu_firmware_info **ucode_list, int ucode_count);
|
||
|
|
void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
|
||
|
|
|
||
|
|
int is_psp_fw_valid(struct psp_bin_desc bin);
|
||
|
|
|
||
|
|
int amdgpu_psp_sysfs_init(struct amdgpu_device *adev);
|
||
|
|
void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev);
|
||
|
|
#endif
|