89 lines
3.0 KiB
C
89 lines
3.0 KiB
C
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "soc21.h"
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#include "gc/gc_11_0_3_offset.h"
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#include "gc/gc_11_0_3_sh_mask.h"
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#include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
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#include "soc15.h"
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#include "soc15d.h"
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#include "gfx_v11_0.h"
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static int gfx_v11_0_3_rlc_gc_fed_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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uint32_t rlc_status0 = 0, rlc_status1 = 0;
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struct ras_common_if *ras_if = NULL;
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struct ras_dispatch_if ih_data = {
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.entry = entry,
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};
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rlc_status0 = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_RLCS_FED_STATUS_0));
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rlc_status1 = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_RLCS_FED_STATUS_1));
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if (!rlc_status0 && !rlc_status1) {
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dev_warn(adev->dev, "RLC_GC_FED irq is generated, but rlc_status0 and rlc_status1 are empty!\n");
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return 0;
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}
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/* Use RLC_RLCS_FED_STATUS_0/1 to distinguish FED error block. */
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if (REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA0_FED_ERR) ||
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REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA1_FED_ERR))
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ras_if = adev->sdma.ras_if;
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else
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ras_if = adev->gfx.ras_if;
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if (!ras_if) {
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dev_err(adev->dev, "Gfx or sdma ras block not initialized, rlc_status0:0x%x.\n",
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rlc_status0);
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return -EINVAL;
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}
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ih_data.head = *ras_if;
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dev_warn(adev->dev, "RLC %s FED IRQ\n", ras_if->name);
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amdgpu_ras_interrupt_dispatch(adev, &ih_data);
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return 0;
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}
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static int gfx_v11_0_3_poison_consumption_handler(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry)
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{
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/* Workaround: when vmid and pasid are both zero, trigger gpu reset in KGD. */
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if (entry && (entry->client_id == SOC21_IH_CLIENTID_GFX) &&
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(entry->src_id == GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT) &&
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!entry->vmid && !entry->pasid)
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amdgpu_ras_reset_gpu(adev);
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return 0;
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}
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struct amdgpu_gfx_ras gfx_v11_0_3_ras = {
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.rlc_gc_fed_irq = gfx_v11_0_3_rlc_gc_fed_irq,
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.poison_consumption_handler = gfx_v11_0_3_poison_consumption_handler,
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};
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