271 lines
8.8 KiB
C
271 lines
8.8 KiB
C
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "sdma/sdma_4_4_0_offset.h"
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#include "sdma/sdma_4_4_0_sh_mask.h"
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#include "soc15.h"
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#include "amdgpu_ras.h"
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#define SDMA1_REG_OFFSET 0x600
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#define SDMA2_REG_OFFSET 0x1cda0
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#define SDMA3_REG_OFFSET 0x1d1a0
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#define SDMA4_REG_OFFSET 0x1d5a0
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/* helper function that allow only use sdma0 register offset
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* to calculate register offset for all the sdma instances */
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static uint32_t sdma_v4_4_get_reg_offset(struct amdgpu_device *adev,
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uint32_t instance,
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uint32_t offset)
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{
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uint32_t sdma_base = adev->reg_offset[SDMA0_HWIP][0][0];
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switch (instance) {
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case 0:
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return (sdma_base + offset);
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case 1:
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return (sdma_base + SDMA1_REG_OFFSET + offset);
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case 2:
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return (sdma_base + SDMA2_REG_OFFSET + offset);
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case 3:
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return (sdma_base + SDMA3_REG_OFFSET + offset);
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case 4:
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return (sdma_base + SDMA4_REG_OFFSET + offset);
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default:
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break;
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}
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return 0;
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}
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static const struct soc15_ras_field_entry sdma_v4_4_ras_fields[] = {
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{ "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED),
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0, 0,
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},
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{ "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED),
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0, 0,
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},
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{ "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_UCODE_BUF_SED),
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0, 0,
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},
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{ "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_RB_CMD_BUF_SED),
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0, 0,
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},
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{ "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_IB_CMD_BUF_SED),
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0, 0,
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},
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{ "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_UTCL1_RD_FIFO_SED),
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0, 0,
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},
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{ "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_UTCL1_RDBST_FIFO_SED),
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0, 0,
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},
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{ "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_DATA_LUT_FIFO_SED),
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0, 0,
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},
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{ "SDMA_SPLIT_DATA_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_SPLIT_DATA_BUF_SED),
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0, 0,
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},
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{ "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_MC_WR_ADDR_FIFO_SED),
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0, 0,
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},
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{ "SDMA_MC_RDRET_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
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SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_MC_WR_ADDR_FIFO_SED),
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0, 0,
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},
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};
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static void sdma_v4_4_get_ras_error_count(struct amdgpu_device *adev,
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uint32_t reg_offset,
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uint32_t value,
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uint32_t instance,
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uint32_t *sec_count)
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{
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uint32_t i;
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uint32_t sec_cnt;
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/* double bits error (multiple bits) error detection is not supported */
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for (i = 0; i < ARRAY_SIZE(sdma_v4_4_ras_fields); i++) {
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if (sdma_v4_4_ras_fields[i].reg_offset != reg_offset)
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continue;
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/* the SDMA_EDC_COUNTER register in each sdma instance
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* shares the same sed shift_mask
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* */
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sec_cnt = (value &
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sdma_v4_4_ras_fields[i].sec_count_mask) >>
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sdma_v4_4_ras_fields[i].sec_count_shift;
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if (sec_cnt) {
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dev_info(adev->dev, "Detected %s in SDMA%d, SED %d\n",
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sdma_v4_4_ras_fields[i].name,
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instance, sec_cnt);
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*sec_count += sec_cnt;
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}
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}
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}
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static int sdma_v4_4_query_ras_error_count_by_instance(struct amdgpu_device *adev,
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uint32_t instance,
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void *ras_error_status)
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{
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struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
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uint32_t sec_count = 0;
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uint32_t reg_value = 0;
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uint32_t reg_offset = 0;
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reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER);
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reg_value = RREG32(reg_offset);
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/* double bit error is not supported */
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if (reg_value)
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sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER, reg_value,
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instance, &sec_count);
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reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER2);
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reg_value = RREG32(reg_offset);
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/* double bit error is not supported */
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if (reg_value)
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sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER2, reg_value,
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instance, &sec_count);
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/*
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* err_data->ue_count should be initialized to 0
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* before calling into this function
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*
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* SDMA RAS supports single bit uncorrectable error detection.
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* So, increment uncorrectable error count.
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*/
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err_data->ue_count += sec_count;
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/*
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* SDMA RAS does not support correctable errors.
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* Set ce count to 0.
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*/
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err_data->ce_count = 0;
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return 0;
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};
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static void sdma_v4_4_reset_ras_error_count(struct amdgpu_device *adev)
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{
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int i;
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uint32_t reg_offset;
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/* write 0 to EDC_COUNTER reg to clear sdma edc counters */
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
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for (i = 0; i < adev->sdma.num_instances; i++) {
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reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER);
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WREG32(reg_offset, 0);
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reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER2);
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WREG32(reg_offset, 0);
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}
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}
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}
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static void sdma_v4_4_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status)
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{
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int i = 0;
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for (i = 0; i < adev->sdma.num_instances; i++) {
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if (sdma_v4_4_query_ras_error_count_by_instance(adev, i, ras_error_status)) {
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dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i);
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return;
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}
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}
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}
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const struct amdgpu_ras_block_hw_ops sdma_v4_4_ras_hw_ops = {
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.query_ras_error_count = sdma_v4_4_query_ras_error_count,
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.reset_ras_error_count = sdma_v4_4_reset_ras_error_count,
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};
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struct amdgpu_sdma_ras sdma_v4_4_ras = {
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.ras_block = {
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.hw_ops = &sdma_v4_4_ras_hw_ops,
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},
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};
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