373 lines
15 KiB
C
373 lines
15 KiB
C
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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright 2016-2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "kfd_priv.h"
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#include "kfd_events.h"
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#include "soc15_int.h"
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#include "kfd_device_queue_manager.h"
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#include "kfd_smi_events.h"
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enum SQ_INTERRUPT_WORD_ENCODING {
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SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,
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SQ_INTERRUPT_WORD_ENCODING_INST,
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SQ_INTERRUPT_WORD_ENCODING_ERROR,
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};
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enum SQ_INTERRUPT_ERROR_TYPE {
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SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0,
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SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST,
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SQ_INTERRUPT_ERROR_TYPE_MEMVIOL,
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SQ_INTERRUPT_ERROR_TYPE_EDC_FED,
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};
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/* SQ_INTERRUPT_WORD_AUTO_CTXID */
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 1
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 2
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 3
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 4
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 5
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 6
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 7
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 8
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 24
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 26
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x00000001
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x00000002
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x00000004
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x00000008
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x00000010
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x00000020
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x00000040
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x00000080
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x00000100
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x03000000
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#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0x0c000000
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/* SQ_INTERRUPT_WORD_WAVE_CTXID */
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 12
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 13
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 14
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 18
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 20
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 24
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 26
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x00000fff
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x00001000
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x00002000
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x0003c000
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x000c0000
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x00f00000
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x03000000
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#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0x0c000000
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#define KFD_CONTEXT_ID_GET_SQ_INT_DATA(ctx0, ctx1) \
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((ctx0 & 0xfff) | ((ctx0 >> 16) & 0xf000) | ((ctx1 << 16) & 0xff0000))
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#define KFD_SQ_INT_DATA__ERR_TYPE_MASK 0xF00000
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#define KFD_SQ_INT_DATA__ERR_TYPE__SHIFT 20
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static void event_interrupt_poison_consumption_v9(struct kfd_dev *dev,
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uint16_t pasid, uint16_t client_id)
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{
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int old_poison, ret = -EINVAL;
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struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
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if (!p)
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return;
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/* all queues of a process will be unmapped in one time */
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old_poison = atomic_cmpxchg(&p->poison, 0, 1);
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kfd_unref_process(p);
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if (old_poison)
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return;
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switch (client_id) {
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case SOC15_IH_CLIENTID_SE0SH:
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case SOC15_IH_CLIENTID_SE1SH:
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case SOC15_IH_CLIENTID_SE2SH:
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case SOC15_IH_CLIENTID_SE3SH:
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case SOC15_IH_CLIENTID_UTCL2:
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ret = kfd_dqm_evict_pasid(dev->dqm, pasid);
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break;
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case SOC15_IH_CLIENTID_SDMA0:
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case SOC15_IH_CLIENTID_SDMA1:
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case SOC15_IH_CLIENTID_SDMA2:
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case SOC15_IH_CLIENTID_SDMA3:
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case SOC15_IH_CLIENTID_SDMA4:
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break;
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default:
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break;
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}
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kfd_signal_poison_consumed_event(dev, pasid);
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/* resetting queue passes, do page retirement without gpu reset
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* resetting queue fails, fallback to gpu reset solution
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*/
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if (!ret) {
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dev_warn(dev->adev->dev,
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"RAS poison consumption, unmap queue flow succeeded: client id %d\n",
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client_id);
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amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, false);
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} else {
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dev_warn(dev->adev->dev,
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"RAS poison consumption, fall back to gpu reset flow: client id %d\n",
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client_id);
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amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, true);
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}
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}
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static bool context_id_expected(struct kfd_dev *dev)
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{
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switch (KFD_GC_VERSION(dev)) {
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case IP_VERSION(9, 0, 1):
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return dev->mec_fw_version >= 0x817a;
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case IP_VERSION(9, 1, 0):
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case IP_VERSION(9, 2, 1):
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case IP_VERSION(9, 2, 2):
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case IP_VERSION(9, 3, 0):
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case IP_VERSION(9, 4, 0):
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return dev->mec_fw_version >= 0x17a;
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default:
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/* Other GFXv9 and later GPUs always sent valid context IDs
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* on legitimate events
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*/
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return KFD_GC_VERSION(dev) >= IP_VERSION(9, 4, 1);
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}
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}
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static bool event_interrupt_isr_v9(struct kfd_dev *dev,
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const uint32_t *ih_ring_entry,
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uint32_t *patched_ihre,
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bool *patched_flag)
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{
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uint16_t source_id, client_id, pasid, vmid;
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const uint32_t *data = ih_ring_entry;
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/* Only handle interrupts from KFD VMIDs */
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vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
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if (vmid < dev->vm_info.first_vmid_kfd ||
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vmid > dev->vm_info.last_vmid_kfd)
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return false;
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source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry);
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client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry);
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pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);
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/* Only handle clients we care about */
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if (client_id != SOC15_IH_CLIENTID_GRBM_CP &&
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client_id != SOC15_IH_CLIENTID_SDMA0 &&
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client_id != SOC15_IH_CLIENTID_SDMA1 &&
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client_id != SOC15_IH_CLIENTID_SDMA2 &&
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client_id != SOC15_IH_CLIENTID_SDMA3 &&
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client_id != SOC15_IH_CLIENTID_SDMA4 &&
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client_id != SOC15_IH_CLIENTID_SDMA5 &&
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client_id != SOC15_IH_CLIENTID_SDMA6 &&
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client_id != SOC15_IH_CLIENTID_SDMA7 &&
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client_id != SOC15_IH_CLIENTID_VMC &&
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client_id != SOC15_IH_CLIENTID_VMC1 &&
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client_id != SOC15_IH_CLIENTID_UTCL2 &&
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client_id != SOC15_IH_CLIENTID_SE0SH &&
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client_id != SOC15_IH_CLIENTID_SE1SH &&
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client_id != SOC15_IH_CLIENTID_SE2SH &&
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client_id != SOC15_IH_CLIENTID_SE3SH)
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return false;
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/* This is a known issue for gfx9. Under non HWS, pasid is not set
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* in the interrupt payload, so we need to find out the pasid on our
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* own.
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*/
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if (!pasid && dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
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const uint32_t pasid_mask = 0xffff;
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*patched_flag = true;
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memcpy(patched_ihre, ih_ring_entry,
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dev->device_info.ih_ring_entry_size);
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pasid = dev->dqm->vmid_pasid[vmid];
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/* Patch the pasid field */
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patched_ihre[3] = cpu_to_le32((le32_to_cpu(patched_ihre[3])
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& ~pasid_mask) | pasid);
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}
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pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",
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client_id, source_id, vmid, pasid);
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pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n",
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data[0], data[1], data[2], data[3],
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data[4], data[5], data[6], data[7]);
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/* If there is no valid PASID, it's likely a bug */
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if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt"))
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return false;
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/* Workaround CP firmware sending bogus signals with 0 context_id.
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* Those can be safely ignored on hardware and firmware versions that
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* include a valid context_id on legitimate signals. This avoids the
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* slow path in kfd_signal_event_interrupt that scans all event slots
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* for signaled events.
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*/
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if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) {
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uint32_t context_id =
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SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry);
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if (context_id == 0 && context_id_expected(dev))
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return false;
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}
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/* Interrupt types we care about: various signals and faults.
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* They will be forwarded to a work queue (see below).
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*/
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return source_id == SOC15_INTSRC_CP_END_OF_PIPE ||
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source_id == SOC15_INTSRC_SDMA_TRAP ||
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source_id == SOC15_INTSRC_SDMA_ECC ||
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source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG ||
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source_id == SOC15_INTSRC_CP_BAD_OPCODE ||
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((client_id == SOC15_IH_CLIENTID_VMC ||
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client_id == SOC15_IH_CLIENTID_VMC1 ||
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client_id == SOC15_IH_CLIENTID_UTCL2) &&
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!amdgpu_no_queue_eviction_on_vm_fault);
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}
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static void event_interrupt_wq_v9(struct kfd_dev *dev,
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const uint32_t *ih_ring_entry)
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{
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uint16_t source_id, client_id, pasid, vmid;
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uint32_t context_id0, context_id1;
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uint32_t sq_intr_err, sq_int_data, encoding;
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source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry);
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client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry);
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pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);
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vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
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context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry);
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context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry);
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if (client_id == SOC15_IH_CLIENTID_GRBM_CP ||
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client_id == SOC15_IH_CLIENTID_SE0SH ||
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client_id == SOC15_IH_CLIENTID_SE1SH ||
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client_id == SOC15_IH_CLIENTID_SE2SH ||
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client_id == SOC15_IH_CLIENTID_SE3SH) {
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if (source_id == SOC15_INTSRC_CP_END_OF_PIPE)
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kfd_signal_event_interrupt(pasid, context_id0, 32);
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else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) {
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sq_int_data = KFD_CONTEXT_ID_GET_SQ_INT_DATA(context_id0, context_id1);
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encoding = REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, ENCODING);
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switch (encoding) {
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case SQ_INTERRUPT_WORD_ENCODING_AUTO:
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pr_debug(
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"sq_intr: auto, se %d, ttrace %d, wlt %d, ttrac_buf_full %d, reg_tms %d, cmd_tms %d, host_cmd_ovf %d, host_reg_ovf %d, immed_ovf %d, ttrace_utc_err %d\n",
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REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, SE_ID),
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REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE),
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REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, WLT),
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REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_BUF_FULL),
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REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, REG_TIMESTAMP),
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REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, CMD_TIMESTAMP),
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REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_CMD_OVERFLOW),
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REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_REG_OVERFLOW),
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REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, IMMED_OVERFLOW),
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_UTC_ERROR));
|
||
|
|
break;
|
||
|
|
case SQ_INTERRUPT_WORD_ENCODING_INST:
|
||
|
|
pr_debug("sq_intr: inst, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, intr_data 0x%x\n",
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID),
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA),
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID),
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV),
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID),
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID),
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID),
|
||
|
|
sq_int_data);
|
||
|
|
break;
|
||
|
|
case SQ_INTERRUPT_WORD_ENCODING_ERROR:
|
||
|
|
sq_intr_err = REG_GET_FIELD(sq_int_data, KFD_SQ_INT_DATA, ERR_TYPE);
|
||
|
|
pr_warn("sq_intr: error, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, err_type %d\n",
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID),
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA),
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID),
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV),
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID),
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID),
|
||
|
|
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID),
|
||
|
|
sq_intr_err);
|
||
|
|
if (sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST &&
|
||
|
|
sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) {
|
||
|
|
event_interrupt_poison_consumption_v9(dev, pasid, client_id);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24);
|
||
|
|
} else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE)
|
||
|
|
kfd_signal_hw_exception_event(pasid);
|
||
|
|
} else if (client_id == SOC15_IH_CLIENTID_SDMA0 ||
|
||
|
|
client_id == SOC15_IH_CLIENTID_SDMA1 ||
|
||
|
|
client_id == SOC15_IH_CLIENTID_SDMA2 ||
|
||
|
|
client_id == SOC15_IH_CLIENTID_SDMA3 ||
|
||
|
|
client_id == SOC15_IH_CLIENTID_SDMA4 ||
|
||
|
|
client_id == SOC15_IH_CLIENTID_SDMA5 ||
|
||
|
|
client_id == SOC15_IH_CLIENTID_SDMA6 ||
|
||
|
|
client_id == SOC15_IH_CLIENTID_SDMA7) {
|
||
|
|
if (source_id == SOC15_INTSRC_SDMA_TRAP) {
|
||
|
|
kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28);
|
||
|
|
} else if (source_id == SOC15_INTSRC_SDMA_ECC) {
|
||
|
|
event_interrupt_poison_consumption_v9(dev, pasid, client_id);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
} else if (client_id == SOC15_IH_CLIENTID_VMC ||
|
||
|
|
client_id == SOC15_IH_CLIENTID_VMC1 ||
|
||
|
|
client_id == SOC15_IH_CLIENTID_UTCL2) {
|
||
|
|
struct kfd_vm_fault_info info = {0};
|
||
|
|
uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry);
|
||
|
|
|
||
|
|
if (client_id == SOC15_IH_CLIENTID_UTCL2 &&
|
||
|
|
amdgpu_amdkfd_ras_query_utcl2_poison_status(dev->adev)) {
|
||
|
|
event_interrupt_poison_consumption_v9(dev, pasid, client_id);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
info.vmid = vmid;
|
||
|
|
info.mc_id = client_id;
|
||
|
|
info.page_addr = ih_ring_entry[4] |
|
||
|
|
(uint64_t)(ih_ring_entry[5] & 0xf) << 32;
|
||
|
|
info.prot_valid = ring_id & 0x08;
|
||
|
|
info.prot_read = ring_id & 0x10;
|
||
|
|
info.prot_write = ring_id & 0x20;
|
||
|
|
|
||
|
|
kfd_smi_event_update_vmfault(dev, pasid);
|
||
|
|
kfd_dqm_evict_pasid(dev->dqm, pasid);
|
||
|
|
kfd_signal_vm_fault_event(dev, pasid, &info);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct kfd_event_interrupt_class event_interrupt_class_v9 = {
|
||
|
|
.interrupt_isr = event_interrupt_isr_v9,
|
||
|
|
.interrupt_wq = event_interrupt_wq_v9,
|
||
|
|
};
|