387 lines
13 KiB
C
387 lines
13 KiB
C
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "reg_helper.h"
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#include "dcn30_optc.h"
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#include "dc.h"
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#include "dcn_calc_math.h"
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#include "dc_dmub_srv.h"
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#include "dml/dcn30/dcn30_fpu.h"
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#include "dc_trace.h"
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#define REG(reg)\
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optc1->tg_regs->reg
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#define CTX \
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optc1->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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optc1->tg_shift->field_name, optc1->tg_mask->field_name
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void optc3_triplebuffer_lock(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_UPDATE(OTG_GLOBAL_CONTROL2,
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OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
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REG_SET(OTG_VUPDATE_KEEPOUT, 0,
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OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
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REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
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OTG_MASTER_UPDATE_LOCK, 1);
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if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
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REG_WAIT(OTG_MASTER_UPDATE_LOCK,
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UPDATE_LOCK_STATUS, 1,
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1, 10);
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TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
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}
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void optc3_lock_doublebuffer_enable(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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uint32_t v_blank_start = 0;
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uint32_t v_blank_end = 0;
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uint32_t h_blank_start = 0;
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uint32_t h_blank_end = 0;
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REG_GET_2(OTG_V_BLANK_START_END,
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OTG_V_BLANK_START, &v_blank_start,
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OTG_V_BLANK_END, &v_blank_end);
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REG_GET_2(OTG_H_BLANK_START_END,
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OTG_H_BLANK_START, &h_blank_start,
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OTG_H_BLANK_END, &h_blank_end);
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REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
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MASTER_UPDATE_LOCK_DB_START_Y, v_blank_start - 1,
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MASTER_UPDATE_LOCK_DB_END_Y, v_blank_start);
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REG_UPDATE_2(OTG_GLOBAL_CONTROL4,
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DIG_UPDATE_POSITION_X, h_blank_start - 180 - 1,
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DIG_UPDATE_POSITION_Y, v_blank_start - 1);
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// there is a DIG_UPDATE_VCOUNT_MODE and it is 0.
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REG_UPDATE_3(OTG_GLOBAL_CONTROL0,
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MASTER_UPDATE_LOCK_DB_START_X, h_blank_start - 200 - 1,
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MASTER_UPDATE_LOCK_DB_END_X, h_blank_start - 180,
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MASTER_UPDATE_LOCK_DB_EN, 1);
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REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
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REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
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MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
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MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100,
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OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
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TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
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}
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void optc3_lock_doublebuffer_disable(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_UPDATE_2(OTG_GLOBAL_CONTROL0,
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MASTER_UPDATE_LOCK_DB_START_X, 0,
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MASTER_UPDATE_LOCK_DB_END_X, 0);
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REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
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MASTER_UPDATE_LOCK_DB_START_Y, 0,
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MASTER_UPDATE_LOCK_DB_END_Y, 0);
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REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
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REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 0);
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TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
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}
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void optc3_lock(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_UPDATE(OTG_GLOBAL_CONTROL2,
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OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
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REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
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OTG_MASTER_UPDATE_LOCK, 1);
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REG_WAIT(OTG_MASTER_UPDATE_LOCK,
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UPDATE_LOCK_STATUS, 1,
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1, 10);
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TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
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}
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void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_UPDATE(OTG_CONTROL, OTG_OUT_MUX, dest);
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}
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void optc3_program_blank_color(struct timing_generator *optc,
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const struct tg_color *blank_color)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_SET_3(OTG_BLANK_DATA_COLOR, 0,
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OTG_BLANK_DATA_COLOR_BLUE_CB, blank_color->color_b_cb,
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OTG_BLANK_DATA_COLOR_GREEN_Y, blank_color->color_g_y,
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OTG_BLANK_DATA_COLOR_RED_CR, blank_color->color_r_cr);
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REG_SET_3(OTG_BLANK_DATA_COLOR_EXT, 0,
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OTG_BLANK_DATA_COLOR_BLUE_CB_EXT, blank_color->color_b_cb >> 10,
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OTG_BLANK_DATA_COLOR_GREEN_Y_EXT, blank_color->color_g_y >> 10,
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OTG_BLANK_DATA_COLOR_RED_CR_EXT, blank_color->color_r_cr >> 10);
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}
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void optc3_set_drr_trigger_window(struct timing_generator *optc,
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uint32_t window_start, uint32_t window_end)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_SET_2(OTG_DRR_TRIGGER_WINDOW, 0,
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OTG_DRR_TRIGGER_WINDOW_START_X, window_start,
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OTG_DRR_TRIGGER_WINDOW_END_X, window_end);
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}
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void optc3_set_vtotal_change_limit(struct timing_generator *optc,
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uint32_t limit)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_SET(OTG_DRR_V_TOTAL_CHANGE, 0,
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OTG_DRR_V_TOTAL_CHANGE_LIMIT, limit);
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}
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/* Set DSC-related configuration.
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* dsc_mode: 0 disables DSC, other values enable DSC in specified format
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* sc_bytes_per_pixel: Bytes per pixel in u3.28 format
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* dsc_slice_width: Slice width in pixels
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*/
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void optc3_set_dsc_config(struct timing_generator *optc,
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enum optc_dsc_mode dsc_mode,
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uint32_t dsc_bytes_per_pixel,
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uint32_t dsc_slice_width)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, dsc_slice_width);
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REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
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}
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void optc3_set_odm_bypass(struct timing_generator *optc,
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const struct dc_crtc_timing *dc_crtc_timing)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
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REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
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OPTC_NUM_OF_INPUT_SEGMENT, 0,
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OPTC_SEG0_SRC_SEL, optc->inst,
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OPTC_SEG1_SRC_SEL, 0xf,
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OPTC_SEG2_SRC_SEL, 0xf,
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OPTC_SEG3_SRC_SEL, 0xf
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);
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h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
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REG_SET(OTG_H_TIMING_CNTL, 0,
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OTG_H_TIMING_DIV_MODE, h_div);
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REG_SET(OPTC_MEMORY_CONFIG, 0,
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OPTC_MEM_SEL, 0);
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optc1->opp_count = 1;
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}
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static void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
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struct dc_crtc_timing *timing)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
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/ opp_cnt;
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uint32_t memory_mask = 0;
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/* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
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* REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
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* Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
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* REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
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* MASTER_UPDATE_LOCK_DB_X, 160,
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* MASTER_UPDATE_LOCK_DB_Y, 240);
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*/
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ASSERT(opp_cnt == 2 || opp_cnt == 4);
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/* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
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* however, for ODM combine we can simplify by always using 4.
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*/
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if (opp_cnt == 2) {
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/* To make sure there's no memory overlap, each instance "reserves" 2
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* memories and they are uniquely combined here.
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*/
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memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
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} else if (opp_cnt == 4) {
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/* To make sure there's no memory overlap, each instance "reserves" 1
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* memory and they are uniquely combined here.
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*/
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memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2) | 0x1 << (opp_id[2] * 2) | 0x1 << (opp_id[3] * 2);
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}
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if (REG(OPTC_MEMORY_CONFIG))
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REG_SET(OPTC_MEMORY_CONFIG, 0,
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OPTC_MEM_SEL, memory_mask);
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if (opp_cnt == 2) {
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REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
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OPTC_NUM_OF_INPUT_SEGMENT, 1,
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OPTC_SEG0_SRC_SEL, opp_id[0],
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OPTC_SEG1_SRC_SEL, opp_id[1]);
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} else if (opp_cnt == 4) {
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REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
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OPTC_NUM_OF_INPUT_SEGMENT, 3,
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OPTC_SEG0_SRC_SEL, opp_id[0],
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OPTC_SEG1_SRC_SEL, opp_id[1],
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OPTC_SEG2_SRC_SEL, opp_id[2],
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OPTC_SEG3_SRC_SEL, opp_id[3]);
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}
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REG_UPDATE(OPTC_WIDTH_CONTROL,
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OPTC_SEGMENT_WIDTH, mpcc_hactive);
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REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
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optc1->opp_count = opp_cnt;
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}
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/**
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* optc3_set_timing_double_buffer() - DRR double buffering control
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*
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* Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
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* VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
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*
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* Options: any time, start of frame, dp start of frame (range timing)
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*/
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static void optc3_set_timing_double_buffer(struct timing_generator *optc, bool enable)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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uint32_t mode = enable ? 2 : 0;
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REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
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OTG_DRR_TIMING_DBUF_UPDATE_MODE, mode);
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}
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void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, 0, 2, 100000); /* 1 vupdate at 5hz */
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}
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void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
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{
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optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max);
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}
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void optc3_tg_init(struct timing_generator *optc)
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{
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optc3_set_timing_double_buffer(optc, true);
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optc1_clear_optc_underflow(optc);
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}
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static struct timing_generator_funcs dcn30_tg_funcs = {
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.validate_timing = optc1_validate_timing,
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.program_timing = optc1_program_timing,
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.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
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.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
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.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
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.program_global_sync = optc1_program_global_sync,
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.enable_crtc = optc2_enable_crtc,
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.disable_crtc = optc1_disable_crtc,
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/* used by enable_timing_synchronization. Not need for FPGA */
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.is_counter_moving = optc1_is_counter_moving,
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.get_position = optc1_get_position,
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.get_frame_count = optc1_get_vblank_counter,
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.get_scanoutpos = optc1_get_crtc_scanoutpos,
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.get_otg_active_size = optc1_get_otg_active_size,
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.set_early_control = optc1_set_early_control,
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/* used by enable_timing_synchronization. Not need for FPGA */
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.wait_for_state = optc1_wait_for_state,
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.set_blank_color = optc3_program_blank_color,
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.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
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.triplebuffer_lock = optc3_triplebuffer_lock,
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.triplebuffer_unlock = optc2_triplebuffer_unlock,
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||
|
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.enable_reset_trigger = optc1_enable_reset_trigger,
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||
|
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.enable_crtc_reset = optc1_enable_crtc_reset,
|
||
|
|
.disable_reset_trigger = optc1_disable_reset_trigger,
|
||
|
|
.lock = optc3_lock,
|
||
|
|
.unlock = optc1_unlock,
|
||
|
|
.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
|
||
|
|
.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
|
||
|
|
.enable_optc_clock = optc1_enable_optc_clock,
|
||
|
|
.set_drr = optc1_set_drr,
|
||
|
|
.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
|
||
|
|
.set_vtotal_min_max = optc3_set_vtotal_min_max,
|
||
|
|
.set_static_screen_control = optc1_set_static_screen_control,
|
||
|
|
.program_stereo = optc1_program_stereo,
|
||
|
|
.is_stereo_left_eye = optc1_is_stereo_left_eye,
|
||
|
|
.tg_init = optc3_tg_init,
|
||
|
|
.is_tg_enabled = optc1_is_tg_enabled,
|
||
|
|
.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
|
||
|
|
.clear_optc_underflow = optc1_clear_optc_underflow,
|
||
|
|
.setup_global_swap_lock = NULL,
|
||
|
|
.get_crc = optc1_get_crc,
|
||
|
|
.configure_crc = optc2_configure_crc,
|
||
|
|
.set_dsc_config = optc3_set_dsc_config,
|
||
|
|
.get_dsc_status = optc2_get_dsc_status,
|
||
|
|
.set_dwb_source = NULL,
|
||
|
|
.set_odm_bypass = optc3_set_odm_bypass,
|
||
|
|
.set_odm_combine = optc3_set_odm_combine,
|
||
|
|
.get_optc_source = optc2_get_optc_source,
|
||
|
|
.set_out_mux = optc3_set_out_mux,
|
||
|
|
.set_drr_trigger_window = optc3_set_drr_trigger_window,
|
||
|
|
.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
|
||
|
|
.set_gsl = optc2_set_gsl,
|
||
|
|
.set_gsl_source_select = optc2_set_gsl_source_select,
|
||
|
|
.set_vtg_params = optc1_set_vtg_params,
|
||
|
|
.program_manual_trigger = optc2_program_manual_trigger,
|
||
|
|
.setup_manual_trigger = optc2_setup_manual_trigger,
|
||
|
|
.get_hw_timing = optc1_get_hw_timing,
|
||
|
|
.wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear,
|
||
|
|
};
|
||
|
|
|
||
|
|
void dcn30_timing_generator_init(struct optc *optc1)
|
||
|
|
{
|
||
|
|
optc1->base.funcs = &dcn30_tg_funcs;
|
||
|
|
|
||
|
|
optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
|
||
|
|
optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
|
||
|
|
|
||
|
|
optc1->min_h_blank = 32;
|
||
|
|
optc1->min_v_blank = 3;
|
||
|
|
optc1->min_v_blank_interlace = 5;
|
||
|
|
optc1->min_h_sync_width = 4;
|
||
|
|
optc1->min_v_sync_width = 1;
|
||
|
|
}
|