112 lines
3.0 KiB
C
112 lines
3.0 KiB
C
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_DCN31_AGP_H__
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#define __DAL_DCN31_AGP_H__
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#define DCN31_APG_FROM_APG(apg)\
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container_of(apg, struct dcn31_apg, base)
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#define APG_DCN31_REG_LIST(id) \
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SRI(APG_CONTROL, APG, id), \
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SRI(APG_CONTROL2, APG, id),\
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SRI(APG_MEM_PWR, APG, id),\
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SRI(APG_DBG_GEN_CONTROL, APG, id)
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struct dcn31_apg_registers {
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uint32_t APG_CONTROL;
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uint32_t APG_CONTROL2;
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uint32_t APG_MEM_PWR;
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uint32_t APG_DBG_GEN_CONTROL;
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};
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#define DCN31_APG_MASK_SH_LIST(mask_sh)\
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SE_SF(APG0_APG_CONTROL, APG_RESET, mask_sh),\
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SE_SF(APG0_APG_CONTROL, APG_RESET_DONE, mask_sh),\
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SE_SF(APG0_APG_CONTROL2, APG_ENABLE, mask_sh),\
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SE_SF(APG0_APG_CONTROL2, APG_DP_AUDIO_STREAM_ID, mask_sh),\
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SE_SF(APG0_APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, mask_sh),\
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SE_SF(APG0_APG_MEM_PWR, APG_MEM_PWR_FORCE, mask_sh)
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#define APG_DCN31_REG_FIELD_LIST(type) \
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type APG_RESET;\
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type APG_RESET_DONE;\
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type APG_ENABLE;\
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type APG_DP_AUDIO_STREAM_ID;\
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type APG_DBG_AUDIO_CHANNEL_ENABLE;\
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type APG_MEM_PWR_FORCE
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struct dcn31_apg_shift {
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APG_DCN31_REG_FIELD_LIST(uint8_t);
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};
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struct dcn31_apg_mask {
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APG_DCN31_REG_FIELD_LIST(uint32_t);
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};
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struct apg {
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const struct apg_funcs *funcs;
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struct dc_context *ctx;
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int inst;
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};
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struct apg_funcs {
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void (*setup_hdmi_audio)(
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struct apg *apg);
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void (*se_audio_setup)(
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struct apg *apg,
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unsigned int az_inst,
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struct audio_info *audio_info);
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void (*enable_apg)(
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struct apg *apg);
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void (*disable_apg)(
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struct apg *apg);
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};
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struct dcn31_apg {
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struct apg base;
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const struct dcn31_apg_registers *regs;
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const struct dcn31_apg_shift *apg_shift;
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const struct dcn31_apg_mask *apg_mask;
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};
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void apg31_construct(struct dcn31_apg *apg3,
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struct dc_context *ctx,
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uint32_t inst,
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const struct dcn31_apg_registers *apg_regs,
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const struct dcn31_apg_shift *apg_shift,
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const struct dcn31_apg_mask *apg_mask);
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#endif
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