254 lines
6.5 KiB
C
254 lines
6.5 KiB
C
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/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "include/gpio_interface.h"
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#include "include/gpio_types.h"
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#include "hw_gpio.h"
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#include "hw_ddc.h"
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#include "reg_helper.h"
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#include "gpio_regs.h"
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#undef FN
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#define FN(reg_name, field_name) \
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ddc->shifts->field_name, ddc->masks->field_name
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#define CTX \
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ddc->base.base.ctx
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#define REG(reg)\
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(ddc->regs->reg)
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struct gpio;
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static void dal_hw_ddc_destruct(
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struct hw_ddc *pin)
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{
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dal_hw_gpio_destruct(&pin->base);
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}
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static void dal_hw_ddc_destroy(
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struct hw_gpio_pin **ptr)
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{
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struct hw_ddc *pin = HW_DDC_FROM_BASE(*ptr);
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dal_hw_ddc_destruct(pin);
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kfree(pin);
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*ptr = NULL;
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}
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static enum gpio_result set_config(
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struct hw_gpio_pin *ptr,
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const struct gpio_config_data *config_data)
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{
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struct hw_ddc *ddc = HW_DDC_FROM_BASE(ptr);
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struct hw_gpio *hw_gpio = NULL;
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uint32_t regval;
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uint32_t ddc_data_pd_en = 0;
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uint32_t ddc_clk_pd_en = 0;
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uint32_t aux_pad_mode = 0;
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hw_gpio = &ddc->base;
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if (hw_gpio == NULL) {
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ASSERT_CRITICAL(false);
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return GPIO_RESULT_NULL_HANDLE;
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}
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regval = REG_GET_3(gpio.MASK_reg,
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DC_GPIO_DDC1DATA_PD_EN, &ddc_data_pd_en,
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DC_GPIO_DDC1CLK_PD_EN, &ddc_clk_pd_en,
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AUX_PAD1_MODE, &aux_pad_mode);
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switch (config_data->config.ddc.type) {
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case GPIO_DDC_CONFIG_TYPE_MODE_I2C:
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/* On plug-in, there is a transient level on the pad
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* which must be discharged through the internal pull-down.
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* Enable internal pull-down, 2.5msec discharge time
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* is required for detection of AUX mode */
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if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) {
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if (!ddc_data_pd_en || !ddc_clk_pd_en) {
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if (hw_gpio->base.en == GPIO_DDC_LINE_DDC_VGA) {
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// bit 4 of mask has different usage in some cases
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REG_SET(gpio.MASK_reg, regval, DC_GPIO_DDC1DATA_PD_EN, 1);
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} else {
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REG_SET_2(gpio.MASK_reg, regval,
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DC_GPIO_DDC1DATA_PD_EN, 1,
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DC_GPIO_DDC1CLK_PD_EN, 1);
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}
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if (config_data->type ==
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GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
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msleep(3);
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}
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} else {
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uint32_t sda_pd_dis = 0;
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uint32_t scl_pd_dis = 0;
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REG_GET_2(gpio.MASK_reg,
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DC_GPIO_SDA_PD_DIS, &sda_pd_dis,
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DC_GPIO_SCL_PD_DIS, &scl_pd_dis);
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if (sda_pd_dis) {
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REG_SET(gpio.MASK_reg, regval,
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DC_GPIO_SDA_PD_DIS, 0);
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if (config_data->type ==
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GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
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msleep(3);
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}
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if (!scl_pd_dis) {
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REG_SET(gpio.MASK_reg, regval,
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DC_GPIO_SCL_PD_DIS, 1);
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if (config_data->type ==
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GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
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msleep(3);
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}
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}
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if (aux_pad_mode) {
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/* let pins to get de-asserted
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* before setting pad to I2C mode */
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if (config_data->config.ddc.data_en_bit_present ||
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config_data->config.ddc.clock_en_bit_present)
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/* [anaumov] in DAL2, there was
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* dc_service_delay_in_microseconds(2000); */
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msleep(2);
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/* set the I2C pad mode */
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/* read the register again,
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* some bits may have been changed */
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REG_UPDATE(gpio.MASK_reg,
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AUX_PAD1_MODE, 0);
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}
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if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) {
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REG_UPDATE(dc_gpio_aux_ctrl_5, DDC_PAD_I2CMODE, 1);
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}
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//set DC_IO_aux_rxsel = 2'b01
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if (ddc->regs->phy_aux_cntl != 0) {
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REG_UPDATE(phy_aux_cntl, AUX_PAD_RXSEL, 1);
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}
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return GPIO_RESULT_OK;
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case GPIO_DDC_CONFIG_TYPE_MODE_AUX:
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/* set the AUX pad mode */
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if (!aux_pad_mode) {
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REG_SET(gpio.MASK_reg, regval,
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AUX_PAD1_MODE, 1);
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}
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if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) {
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REG_UPDATE(dc_gpio_aux_ctrl_5,
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DDC_PAD_I2CMODE, 0);
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}
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return GPIO_RESULT_OK;
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case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT:
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if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
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(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
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REG_UPDATE_3(ddc_setup,
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DC_I2C_DDC1_ENABLE, 1,
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DC_I2C_DDC1_EDID_DETECT_ENABLE, 1,
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DC_I2C_DDC1_EDID_DETECT_MODE, 0);
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return GPIO_RESULT_OK;
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}
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break;
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case GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT:
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if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
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(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
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REG_UPDATE_3(ddc_setup,
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DC_I2C_DDC1_ENABLE, 1,
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DC_I2C_DDC1_EDID_DETECT_ENABLE, 1,
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DC_I2C_DDC1_EDID_DETECT_MODE, 1);
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return GPIO_RESULT_OK;
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}
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break;
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case GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING:
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if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
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(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
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REG_UPDATE_2(ddc_setup,
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DC_I2C_DDC1_ENABLE, 0,
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DC_I2C_DDC1_EDID_DETECT_ENABLE, 0);
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return GPIO_RESULT_OK;
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}
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break;
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}
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BREAK_TO_DEBUGGER();
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return GPIO_RESULT_NON_SPECIFIC_ERROR;
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}
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static const struct hw_gpio_pin_funcs funcs = {
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.destroy = dal_hw_ddc_destroy,
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.open = dal_hw_gpio_open,
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.get_value = dal_hw_gpio_get_value,
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.set_value = dal_hw_gpio_set_value,
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.set_config = set_config,
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.change_mode = dal_hw_gpio_change_mode,
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.close = dal_hw_gpio_close,
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};
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static void dal_hw_ddc_construct(
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struct hw_ddc *ddc,
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enum gpio_id id,
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uint32_t en,
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struct dc_context *ctx)
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{
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dal_hw_gpio_construct(&ddc->base, id, en, ctx);
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ddc->base.base.funcs = &funcs;
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}
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void dal_hw_ddc_init(
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struct hw_ddc **hw_ddc,
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struct dc_context *ctx,
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enum gpio_id id,
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uint32_t en)
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{
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if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
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ASSERT_CRITICAL(false);
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*hw_ddc = NULL;
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}
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*hw_ddc = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL);
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if (!*hw_ddc) {
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ASSERT_CRITICAL(false);
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return;
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}
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dal_hw_ddc_construct(*hw_ddc, id, en, ctx);
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}
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struct hw_gpio_pin *dal_hw_ddc_get_pin(struct gpio *gpio)
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{
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struct hw_ddc *hw_ddc = dal_gpio_get_ddc(gpio);
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return &hw_ddc->base.base;
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}
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