299 lines
9.6 KiB
C
299 lines
9.6 KiB
C
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* This file defines the private interface between the
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* AMD kernel graphics drivers and the AMD KFD.
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*/
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#ifndef KGD_KFD_INTERFACE_H_INCLUDED
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#define KGD_KFD_INTERFACE_H_INCLUDED
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#include <linux/types.h>
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#include <linux/bitmap.h>
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#include <linux/dma-fence.h>
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struct pci_dev;
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struct amdgpu_device;
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#define KGD_MAX_QUEUES 128
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struct kfd_dev;
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struct kgd_mem;
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enum kfd_preempt_type {
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KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN = 0,
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KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
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KFD_PREEMPT_TYPE_WAVEFRONT_SAVE
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};
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struct kfd_vm_fault_info {
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uint64_t page_addr;
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uint32_t vmid;
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uint32_t mc_id;
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uint32_t status;
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bool prot_valid;
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bool prot_read;
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bool prot_write;
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bool prot_exec;
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};
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struct kfd_cu_info {
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uint32_t num_shader_engines;
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uint32_t num_shader_arrays_per_engine;
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uint32_t num_cu_per_sh;
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uint32_t cu_active_number;
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uint32_t cu_ao_mask;
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uint32_t simd_per_cu;
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uint32_t max_waves_per_simd;
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uint32_t wave_front_size;
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uint32_t max_scratch_slots_per_cu;
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uint32_t lds_size;
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uint32_t cu_bitmap[4][4];
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};
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/* For getting GPU local memory information from KGD */
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struct kfd_local_mem_info {
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uint64_t local_mem_size_private;
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uint64_t local_mem_size_public;
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uint32_t vram_width;
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uint32_t mem_clk_max;
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};
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enum kgd_memory_pool {
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KGD_POOL_SYSTEM_CACHEABLE = 1,
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KGD_POOL_SYSTEM_WRITECOMBINE = 2,
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KGD_POOL_FRAMEBUFFER = 3,
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};
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/**
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* enum kfd_sched_policy
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*
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* @KFD_SCHED_POLICY_HWS: H/W scheduling policy known as command processor (cp)
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* scheduling. In this scheduling mode we're using the firmware code to
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* schedule the user mode queues and kernel queues such as HIQ and DIQ.
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* the HIQ queue is used as a special queue that dispatches the configuration
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* to the cp and the user mode queues list that are currently running.
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* the DIQ queue is a debugging queue that dispatches debugging commands to the
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* firmware.
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* in this scheduling mode user mode queues over subscription feature is
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* enabled.
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*
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* @KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: The same as above but the over
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* subscription feature disabled.
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*
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* @KFD_SCHED_POLICY_NO_HWS: no H/W scheduling policy is a mode which directly
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* set the command processor registers and sets the queues "manually". This
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* mode is used *ONLY* for debugging proposes.
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*
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*/
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enum kfd_sched_policy {
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KFD_SCHED_POLICY_HWS = 0,
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KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION,
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KFD_SCHED_POLICY_NO_HWS
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};
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struct kgd2kfd_shared_resources {
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/* Bit n == 1 means VMID n is available for KFD. */
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unsigned int compute_vmid_bitmap;
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/* number of pipes per mec */
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uint32_t num_pipe_per_mec;
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/* number of queues per pipe */
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uint32_t num_queue_per_pipe;
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/* Bit n == 1 means Queue n is available for KFD */
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DECLARE_BITMAP(cp_queue_bitmap, KGD_MAX_QUEUES);
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/* SDMA doorbell assignments (SOC15 and later chips only). Only
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* specific doorbells are routed to each SDMA engine. Others
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* are routed to IH and VCN. They are not usable by the CP.
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*/
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uint32_t *sdma_doorbell_idx;
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/* From SOC15 onward, the doorbell index range not usable for CP
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* queues.
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*/
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uint32_t non_cp_doorbells_start;
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uint32_t non_cp_doorbells_end;
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/* Base address of doorbell aperture. */
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phys_addr_t doorbell_physical_address;
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/* Size in bytes of doorbell aperture. */
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size_t doorbell_aperture_size;
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/* Number of bytes at start of aperture reserved for KGD. */
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size_t doorbell_start_offset;
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/* GPUVM address space size in bytes */
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uint64_t gpuvm_size;
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/* Minor device number of the render node */
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int drm_render_minor;
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bool enable_mes;
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};
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struct tile_config {
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uint32_t *tile_config_ptr;
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uint32_t *macro_tile_config_ptr;
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uint32_t num_tile_configs;
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uint32_t num_macro_tile_configs;
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uint32_t gb_addr_config;
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uint32_t num_banks;
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uint32_t num_ranks;
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};
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#define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT 4096
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/**
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* struct kfd2kgd_calls
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*
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* @program_sh_mem_settings: A function that should initiate the memory
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* properties such as main aperture memory type (cache / non cached) and
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* secondary aperture base address, size and memory type.
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* This function is used only for no cp scheduling mode.
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*
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* @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp
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* scheduling mode. Only used for no cp scheduling mode.
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*
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* @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp
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* sceduling mode.
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*
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* @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot.
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* used only for no HWS mode.
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*
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* @hqd_dump: Dumps CPC HQD registers to an array of address-value pairs.
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* Array is allocated with kmalloc, needs to be freed with kfree by caller.
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*
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* @hqd_sdma_dump: Dumps SDMA HQD registers to an array of address-value pairs.
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* Array is allocated with kmalloc, needs to be freed with kfree by caller.
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*
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* @hqd_is_occupies: Checks if a hqd slot is occupied.
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*
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* @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot.
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*
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* @hqd_sdma_is_occupied: Checks if an SDMA hqd slot is occupied.
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*
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* @hqd_sdma_destroy: Destructs and preempts the SDMA queue assigned to that
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* SDMA hqd slot.
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*
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* @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID.
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* Only used for no cp scheduling mode
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*
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* @set_vm_context_page_table_base: Program page table base for a VMID
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*
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* @invalidate_tlbs: Invalidate TLBs for a specific PASID
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*
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* @invalidate_tlbs_vmid: Invalidate TLBs for a specific VMID
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*
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* @read_vmid_from_vmfault_reg: On Hawaii the VMID is not set in the
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* IH ring entry. This function allows the KFD ISR to get the VMID
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* from the fault status register as early as possible.
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*
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* @get_cu_occupancy: Function pointer that returns to caller the number
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* of wave fronts that are in flight for all of the queues of a process
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* as identified by its pasid. It is important to note that the value
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* returned by this function is a snapshot of current moment and cannot
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* guarantee any minimum for the number of waves in-flight. This function
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* is defined for devices that belong to GFX9 and later GFX families. Care
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* must be taken in calling this function as it is not defined for devices
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* that belong to GFX8 and below GFX families.
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*
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* This structure contains function pointers to services that the kgd driver
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* provides to amdkfd driver.
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*
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*/
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struct kfd2kgd_calls {
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/* Register access functions */
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void (*program_sh_mem_settings)(struct amdgpu_device *adev, uint32_t vmid,
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uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
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uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
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int (*set_pasid_vmid_mapping)(struct amdgpu_device *adev, u32 pasid,
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unsigned int vmid);
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int (*init_interrupts)(struct amdgpu_device *adev, uint32_t pipe_id);
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int (*hqd_load)(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,
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uint32_t queue_id, uint32_t __user *wptr,
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uint32_t wptr_shift, uint32_t wptr_mask,
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struct mm_struct *mm);
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int (*hiq_mqd_load)(struct amdgpu_device *adev, void *mqd,
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uint32_t pipe_id, uint32_t queue_id,
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uint32_t doorbell_off);
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int (*hqd_sdma_load)(struct amdgpu_device *adev, void *mqd,
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uint32_t __user *wptr, struct mm_struct *mm);
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int (*hqd_dump)(struct amdgpu_device *adev,
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uint32_t pipe_id, uint32_t queue_id,
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uint32_t (**dump)[2], uint32_t *n_regs);
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int (*hqd_sdma_dump)(struct amdgpu_device *adev,
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uint32_t engine_id, uint32_t queue_id,
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uint32_t (**dump)[2], uint32_t *n_regs);
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bool (*hqd_is_occupied)(struct amdgpu_device *adev,
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uint64_t queue_address, uint32_t pipe_id,
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uint32_t queue_id);
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int (*hqd_destroy)(struct amdgpu_device *adev, void *mqd,
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enum kfd_preempt_type reset_type,
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unsigned int timeout, uint32_t pipe_id,
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uint32_t queue_id);
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bool (*hqd_sdma_is_occupied)(struct amdgpu_device *adev, void *mqd);
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int (*hqd_sdma_destroy)(struct amdgpu_device *adev, void *mqd,
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unsigned int timeout);
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int (*wave_control_execute)(struct amdgpu_device *adev,
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uint32_t gfx_index_val,
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uint32_t sq_cmd);
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bool (*get_atc_vmid_pasid_mapping_info)(struct amdgpu_device *adev,
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uint8_t vmid,
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uint16_t *p_pasid);
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/* No longer needed from GFXv9 onward. The scratch base address is
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* passed to the shader by the CP. It's the user mode driver's
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* responsibility.
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*/
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void (*set_scratch_backing_va)(struct amdgpu_device *adev,
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uint64_t va, uint32_t vmid);
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void (*set_vm_context_page_table_base)(struct amdgpu_device *adev,
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uint32_t vmid, uint64_t page_table_base);
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uint32_t (*read_vmid_from_vmfault_reg)(struct amdgpu_device *adev);
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void (*get_cu_occupancy)(struct amdgpu_device *adev, int pasid,
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int *wave_cnt, int *max_waves_per_cu);
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void (*program_trap_handler_settings)(struct amdgpu_device *adev,
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uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr);
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};
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#endif /* KGD_KFD_INTERFACE_H_INCLUDED */
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