355 lines
9.7 KiB
C
355 lines
9.7 KiB
C
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "vega20_thermal.h"
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#include "vega20_hwmgr.h"
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#include "vega20_smumgr.h"
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#include "vega20_ppsmc.h"
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#include "vega20_inc.h"
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#include "soc15_common.h"
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#include "pp_debug.h"
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static int vega20_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
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{
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struct vega20_hwmgr *data = hwmgr->backend;
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int ret = 0;
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if (data->smu_features[GNLD_FAN_CONTROL].supported) {
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ret = vega20_enable_smc_features(
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hwmgr, false,
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data->smu_features[GNLD_FAN_CONTROL].
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smu_feature_bitmap);
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PP_ASSERT_WITH_CODE(!ret,
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"Disable FAN CONTROL feature Failed!",
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return ret);
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data->smu_features[GNLD_FAN_CONTROL].enabled = false;
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}
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return ret;
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}
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int vega20_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
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{
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struct vega20_hwmgr *data = hwmgr->backend;
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if (data->smu_features[GNLD_FAN_CONTROL].supported)
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return vega20_disable_fan_control_feature(hwmgr);
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return 0;
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}
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static int vega20_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
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{
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struct vega20_hwmgr *data = hwmgr->backend;
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int ret = 0;
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if (data->smu_features[GNLD_FAN_CONTROL].supported) {
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ret = vega20_enable_smc_features(
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hwmgr, true,
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data->smu_features[GNLD_FAN_CONTROL].
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smu_feature_bitmap);
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PP_ASSERT_WITH_CODE(!ret,
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"Enable FAN CONTROL feature Failed!",
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return ret);
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data->smu_features[GNLD_FAN_CONTROL].enabled = true;
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}
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return ret;
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}
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int vega20_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
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{
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struct vega20_hwmgr *data = hwmgr->backend;
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if (data->smu_features[GNLD_FAN_CONTROL].supported)
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return vega20_enable_fan_control_feature(hwmgr);
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return 0;
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}
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static int vega20_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
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REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
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CG_FDO_CTRL2, TMIN, 0));
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WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
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REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
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CG_FDO_CTRL2, FDO_PWM_MODE, mode));
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return 0;
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}
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static int vega20_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
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{
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int ret = 0;
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PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
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PPSMC_MSG_GetCurrentRpm,
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current_rpm)) == 0,
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"Attempt to get current RPM from SMC Failed!",
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return ret);
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return 0;
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}
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int vega20_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr,
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uint32_t *speed)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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uint32_t duty100, duty;
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uint64_t tmp64;
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duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
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CG_FDO_CTRL1, FMAX_DUTY100);
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duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
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CG_THERMAL_STATUS, FDO_PWM_DUTY);
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if (!duty100)
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return -EINVAL;
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tmp64 = (uint64_t)duty * 255;
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do_div(tmp64, duty100);
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*speed = MIN((uint32_t)tmp64, 255);
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return 0;
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}
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int vega20_fan_ctrl_set_fan_speed_pwm(struct pp_hwmgr *hwmgr,
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uint32_t speed)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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uint32_t duty100;
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uint32_t duty;
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uint64_t tmp64;
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speed = MIN(speed, 255);
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if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
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vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
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duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
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CG_FDO_CTRL1, FMAX_DUTY100);
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if (duty100 == 0)
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return -EINVAL;
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tmp64 = (uint64_t)speed * duty100;
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do_div(tmp64, 255);
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duty = (uint32_t)tmp64;
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WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
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REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
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CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
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return vega20_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
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}
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int vega20_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
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struct phm_fan_speed_info *fan_speed_info)
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{
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memset(fan_speed_info, 0, sizeof(*fan_speed_info));
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fan_speed_info->supports_percent_read = true;
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fan_speed_info->supports_percent_write = true;
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fan_speed_info->supports_rpm_read = true;
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fan_speed_info->supports_rpm_write = true;
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return 0;
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}
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int vega20_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
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{
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*speed = 0;
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return vega20_get_current_rpm(hwmgr, speed);
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}
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int vega20_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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uint32_t tach_period, crystal_clock_freq;
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int result = 0;
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if (!speed)
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return -EINVAL;
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if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {
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result = vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
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if (result)
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return result;
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}
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crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
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tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
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WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
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REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
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CG_TACH_CTRL, TARGET_PERIOD,
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tach_period));
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return vega20_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
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}
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/**
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* vega20_thermal_get_temperature - Reads the remote temperature from the SIslands thermal controller.
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*
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* @hwmgr: The address of the hardware manager.
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*/
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int vega20_thermal_get_temperature(struct pp_hwmgr *hwmgr)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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int temp = 0;
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temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
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temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
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CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
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temp = temp & 0x1ff;
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temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
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return temp;
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}
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/**
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* vega20_thermal_set_temperature_range - Set the requested temperature range for high and low alert signals
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*
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* @hwmgr: The address of the hardware manager.
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* @range: Temperature range to be programmed for high and low alert signals
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* Exception: PP_Result_BadInput if the input data is not valid.
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*/
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static int vega20_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
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struct PP_TemperatureRange *range)
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{
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struct phm_ppt_v3_information *pptable_information =
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(struct phm_ppt_v3_information *)hwmgr->pptable;
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struct amdgpu_device *adev = hwmgr->adev;
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int low = VEGA20_THERMAL_MINIMUM_ALERT_TEMP;
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int high = VEGA20_THERMAL_MAXIMUM_ALERT_TEMP;
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uint32_t val;
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/* compare them in unit celsius degree */
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if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
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low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
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if (high > pptable_information->us_software_shutdown_temp)
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high = pptable_information->us_software_shutdown_temp;
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if (low > high)
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return -EINVAL;
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val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
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val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
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val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
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val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
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val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
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val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
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WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
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return 0;
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}
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/**
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* vega20_thermal_enable_alert - Enable thermal alerts on the RV770 thermal controller.
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*
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* @hwmgr: The address of the hardware manager.
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*/
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static int vega20_thermal_enable_alert(struct pp_hwmgr *hwmgr)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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uint32_t val = 0;
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val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
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val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
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val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
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WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
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return 0;
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}
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/**
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* vega20_thermal_disable_alert - Disable thermal alerts on the RV770 thermal controller.
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* @hwmgr: The address of the hardware manager.
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*/
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int vega20_thermal_disable_alert(struct pp_hwmgr *hwmgr)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
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return 0;
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}
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/**
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* vega20_thermal_stop_thermal_controller - Uninitialize the thermal controller.
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* Currently just disables alerts.
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* @hwmgr: The address of the hardware manager.
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*/
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int vega20_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
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{
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int result = vega20_thermal_disable_alert(hwmgr);
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return result;
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}
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/**
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* vega20_thermal_setup_fan_table - Set up the fan table to control the fan using the SMC.
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* @hwmgr: the address of the powerplay hardware manager.
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*/
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static int vega20_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
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{
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int ret;
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struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
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PPTable_t *table = &(data->smc_state_table.pp_table);
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ret = smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetFanTemperatureTarget,
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(uint32_t)table->FanTargetTemperature,
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NULL);
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return ret;
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}
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int vega20_start_thermal_controller(struct pp_hwmgr *hwmgr,
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struct PP_TemperatureRange *range)
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{
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int ret = 0;
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if (range == NULL)
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return -EINVAL;
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ret = vega20_thermal_set_temperature_range(hwmgr, range);
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if (ret)
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return ret;
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ret = vega20_thermal_enable_alert(hwmgr);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
ret = vega20_thermal_setup_fan_table(hwmgr);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
};
|