417 lines
10 KiB
C
417 lines
10 KiB
C
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/*
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* Copyright (C) 2013-2015 ARM Limited
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* Author: Liviu Dudau <Liviu.Dudau@arm.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*
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* ARM HDLCD Driver
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*/
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/console.h>
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#include <linux/dma-mapping.h>
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#include <linux/list.h>
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#include <linux/of_graph.h>
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#include <linux/of_reserved_mem.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <drm/drm_aperture.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_debugfs.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_fbdev_generic.h>
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#include <drm/drm_gem_dma_helper.h>
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#include <drm/drm_gem_framebuffer_helper.h>
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#include <drm/drm_modeset_helper.h>
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#include <drm/drm_module.h>
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#include <drm/drm_of.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_vblank.h>
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#include "hdlcd_drv.h"
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#include "hdlcd_regs.h"
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static irqreturn_t hdlcd_irq(int irq, void *arg)
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{
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struct hdlcd_drm_private *hdlcd = arg;
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unsigned long irq_status;
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irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
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#ifdef CONFIG_DEBUG_FS
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if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
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atomic_inc(&hdlcd->buffer_underrun_count);
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if (irq_status & HDLCD_INTERRUPT_DMA_END)
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atomic_inc(&hdlcd->dma_end_count);
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if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
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atomic_inc(&hdlcd->bus_error_count);
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if (irq_status & HDLCD_INTERRUPT_VSYNC)
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atomic_inc(&hdlcd->vsync_count);
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#endif
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if (irq_status & HDLCD_INTERRUPT_VSYNC)
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drm_crtc_handle_vblank(&hdlcd->crtc);
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/* acknowledge interrupt(s) */
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hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
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return IRQ_HANDLED;
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}
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static int hdlcd_irq_install(struct hdlcd_drm_private *hdlcd)
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{
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int ret;
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/* Ensure interrupts are disabled */
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hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
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hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
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ret = request_irq(hdlcd->irq, hdlcd_irq, 0, "hdlcd", hdlcd);
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if (ret)
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return ret;
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#ifdef CONFIG_DEBUG_FS
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/* enable debug interrupts */
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hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, HDLCD_DEBUG_INT_MASK);
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#endif
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return 0;
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}
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static void hdlcd_irq_uninstall(struct hdlcd_drm_private *hdlcd)
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{
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/* disable all the interrupts that we might have enabled */
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hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
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free_irq(hdlcd->irq, hdlcd);
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}
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static int hdlcd_load(struct drm_device *drm, unsigned long flags)
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{
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struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
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struct platform_device *pdev = to_platform_device(drm->dev);
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struct resource *res;
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u32 version;
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int ret;
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hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
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if (IS_ERR(hdlcd->clk))
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return PTR_ERR(hdlcd->clk);
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#ifdef CONFIG_DEBUG_FS
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atomic_set(&hdlcd->buffer_underrun_count, 0);
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atomic_set(&hdlcd->bus_error_count, 0);
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atomic_set(&hdlcd->vsync_count, 0);
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atomic_set(&hdlcd->dma_end_count, 0);
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#endif
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
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if (IS_ERR(hdlcd->mmio)) {
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DRM_ERROR("failed to map control registers area\n");
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ret = PTR_ERR(hdlcd->mmio);
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hdlcd->mmio = NULL;
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return ret;
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}
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version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
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if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
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DRM_ERROR("unknown product id: 0x%x\n", version);
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return -EINVAL;
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}
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DRM_INFO("found ARM HDLCD version r%dp%d\n",
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(version & HDLCD_VERSION_MAJOR_MASK) >> 8,
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version & HDLCD_VERSION_MINOR_MASK);
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/* Get the optional framebuffer memory resource */
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ret = of_reserved_mem_device_init(drm->dev);
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if (ret && ret != -ENODEV)
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return ret;
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ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
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if (ret)
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goto setup_fail;
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ret = hdlcd_setup_crtc(drm);
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if (ret < 0) {
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DRM_ERROR("failed to create crtc\n");
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goto setup_fail;
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}
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ret = platform_get_irq(pdev, 0);
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if (ret < 0)
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goto irq_fail;
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hdlcd->irq = ret;
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ret = hdlcd_irq_install(hdlcd);
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if (ret < 0) {
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DRM_ERROR("failed to install IRQ handler\n");
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goto irq_fail;
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}
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return 0;
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irq_fail:
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drm_crtc_cleanup(&hdlcd->crtc);
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setup_fail:
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of_reserved_mem_device_release(drm->dev);
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return ret;
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}
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static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
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.fb_create = drm_gem_fb_create,
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.atomic_check = drm_atomic_helper_check,
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.atomic_commit = drm_atomic_helper_commit,
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};
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static int hdlcd_setup_mode_config(struct drm_device *drm)
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{
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int ret;
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ret = drmm_mode_config_init(drm);
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if (ret)
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return ret;
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drm->mode_config.min_width = 0;
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drm->mode_config.min_height = 0;
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drm->mode_config.max_width = HDLCD_MAX_XRES;
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drm->mode_config.max_height = HDLCD_MAX_YRES;
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drm->mode_config.funcs = &hdlcd_mode_config_funcs;
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return 0;
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}
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#ifdef CONFIG_DEBUG_FS
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static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
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{
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struct drm_debugfs_entry *entry = m->private;
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struct drm_device *drm = entry->dev;
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struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
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seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
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seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
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seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
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seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
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return 0;
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}
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static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
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{
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struct drm_debugfs_entry *entry = m->private;
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struct drm_device *drm = entry->dev;
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struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
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unsigned long clkrate = clk_get_rate(hdlcd->clk);
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unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
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seq_printf(m, "hw : %lu\n", clkrate);
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seq_printf(m, "mode: %lu\n", mode_clock);
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return 0;
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}
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static struct drm_debugfs_info hdlcd_debugfs_list[] = {
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{ "interrupt_count", hdlcd_show_underrun_count, 0 },
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{ "clocks", hdlcd_show_pxlclock, 0 },
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};
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#endif
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DEFINE_DRM_GEM_DMA_FOPS(fops);
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static const struct drm_driver hdlcd_driver = {
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.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
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DRM_GEM_DMA_DRIVER_OPS,
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.fops = &fops,
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.name = "hdlcd",
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.desc = "ARM HDLCD Controller DRM",
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.date = "20151021",
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.major = 1,
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.minor = 0,
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};
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static int hdlcd_drm_bind(struct device *dev)
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{
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struct drm_device *drm;
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struct hdlcd_drm_private *hdlcd;
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int ret;
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hdlcd = devm_drm_dev_alloc(dev, &hdlcd_driver, typeof(*hdlcd), base);
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if (IS_ERR(hdlcd))
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return PTR_ERR(hdlcd);
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drm = &hdlcd->base;
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dev_set_drvdata(dev, drm);
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ret = hdlcd_setup_mode_config(drm);
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if (ret)
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goto err_free;
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ret = hdlcd_load(drm, 0);
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if (ret)
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goto err_free;
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/* Set the CRTC's port so that the encoder component can find it */
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hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
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ret = component_bind_all(dev, drm);
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if (ret) {
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DRM_ERROR("Failed to bind all components\n");
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goto err_unload;
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}
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ret = pm_runtime_set_active(dev);
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if (ret)
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goto err_pm_active;
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pm_runtime_enable(dev);
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ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
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if (ret < 0) {
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DRM_ERROR("failed to initialise vblank\n");
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goto err_vblank;
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}
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/*
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* If EFI left us running, take over from simple framebuffer
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* drivers. Read HDLCD_REG_COMMAND to see if we are enabled.
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*/
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if (hdlcd_read(hdlcd, HDLCD_REG_COMMAND)) {
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hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
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drm_aperture_remove_framebuffers(false, &hdlcd_driver);
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}
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drm_mode_config_reset(drm);
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drm_kms_helper_poll_init(drm);
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#ifdef CONFIG_DEBUG_FS
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drm_debugfs_add_files(drm, hdlcd_debugfs_list, ARRAY_SIZE(hdlcd_debugfs_list));
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#endif
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ret = drm_dev_register(drm, 0);
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if (ret)
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goto err_register;
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drm_fbdev_generic_setup(drm, 32);
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return 0;
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err_register:
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drm_kms_helper_poll_fini(drm);
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err_vblank:
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pm_runtime_disable(drm->dev);
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err_pm_active:
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drm_atomic_helper_shutdown(drm);
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component_unbind_all(dev, drm);
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err_unload:
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of_node_put(hdlcd->crtc.port);
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hdlcd->crtc.port = NULL;
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hdlcd_irq_uninstall(hdlcd);
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of_reserved_mem_device_release(drm->dev);
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err_free:
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dev_set_drvdata(dev, NULL);
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return ret;
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}
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static void hdlcd_drm_unbind(struct device *dev)
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{
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struct drm_device *drm = dev_get_drvdata(dev);
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struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
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drm_dev_unregister(drm);
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drm_kms_helper_poll_fini(drm);
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component_unbind_all(dev, drm);
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of_node_put(hdlcd->crtc.port);
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hdlcd->crtc.port = NULL;
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pm_runtime_get_sync(dev);
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drm_atomic_helper_shutdown(drm);
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hdlcd_irq_uninstall(hdlcd);
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pm_runtime_put(dev);
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if (pm_runtime_enabled(dev))
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pm_runtime_disable(dev);
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of_reserved_mem_device_release(dev);
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dev_set_drvdata(dev, NULL);
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}
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static const struct component_master_ops hdlcd_master_ops = {
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.bind = hdlcd_drm_bind,
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.unbind = hdlcd_drm_unbind,
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};
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static int compare_dev(struct device *dev, void *data)
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{
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return dev->of_node == data;
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}
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static int hdlcd_probe(struct platform_device *pdev)
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{
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struct device_node *port;
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struct component_match *match = NULL;
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/* there is only one output port inside each device, find it */
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port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
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if (!port)
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return -ENODEV;
|
||
|
|
|
||
|
|
drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
|
||
|
|
of_node_put(port);
|
||
|
|
|
||
|
|
return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
|
||
|
|
match);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int hdlcd_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
component_master_del(&pdev->dev, &hdlcd_master_ops);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id hdlcd_of_match[] = {
|
||
|
|
{ .compatible = "arm,hdlcd" },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, hdlcd_of_match);
|
||
|
|
|
||
|
|
static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
|
||
|
|
{
|
||
|
|
struct drm_device *drm = dev_get_drvdata(dev);
|
||
|
|
|
||
|
|
return drm_mode_config_helper_suspend(drm);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __maybe_unused hdlcd_pm_resume(struct device *dev)
|
||
|
|
{
|
||
|
|
struct drm_device *drm = dev_get_drvdata(dev);
|
||
|
|
|
||
|
|
drm_mode_config_helper_resume(drm);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
|
||
|
|
|
||
|
|
static struct platform_driver hdlcd_platform_driver = {
|
||
|
|
.probe = hdlcd_probe,
|
||
|
|
.remove = hdlcd_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "hdlcd",
|
||
|
|
.pm = &hdlcd_pm_ops,
|
||
|
|
.of_match_table = hdlcd_of_match,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
drm_module_platform_driver(hdlcd_platform_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Liviu Dudau");
|
||
|
|
MODULE_DESCRIPTION("ARM HDLCD DRM driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|