620 lines
15 KiB
C
620 lines
15 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Chrontel CH7033 Video Encoder Driver
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*
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* Copyright (C) 2019,2020 Lubomir Rintel
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*/
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_of.h>
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#include <drm/drm_print.h>
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#include <drm/drm_probe_helper.h>
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/* Page 0, Register 0x07 */
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enum {
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DRI_PD = BIT(3),
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IO_PD = BIT(5),
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};
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/* Page 0, Register 0x08 */
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enum {
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DRI_PDDRI = GENMASK(7, 4),
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PDDAC = GENMASK(3, 1),
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PANEN = BIT(0),
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};
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/* Page 0, Register 0x09 */
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enum {
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DPD = BIT(7),
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GCKOFF = BIT(6),
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TV_BP = BIT(5),
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SCLPD = BIT(4),
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SDPD = BIT(3),
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VGA_PD = BIT(2),
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HDBKPD = BIT(1),
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HDMI_PD = BIT(0),
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};
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/* Page 0, Register 0x0a */
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enum {
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MEMINIT = BIT(7),
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MEMIDLE = BIT(6),
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MEMPD = BIT(5),
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STOP = BIT(4),
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LVDS_PD = BIT(3),
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HD_DVIB = BIT(2),
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HDCP_PD = BIT(1),
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MCU_PD = BIT(0),
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};
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/* Page 0, Register 0x18 */
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enum {
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IDF = GENMASK(7, 4),
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INTEN = BIT(3),
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SWAP = GENMASK(2, 0),
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};
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enum {
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BYTE_SWAP_RGB = 0,
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BYTE_SWAP_RBG = 1,
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BYTE_SWAP_GRB = 2,
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BYTE_SWAP_GBR = 3,
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BYTE_SWAP_BRG = 4,
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BYTE_SWAP_BGR = 5,
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};
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/* Page 0, Register 0x19 */
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enum {
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HPO_I = BIT(5),
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VPO_I = BIT(4),
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DEPO_I = BIT(3),
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CRYS_EN = BIT(2),
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GCLKFREQ = GENMASK(2, 0),
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};
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/* Page 0, Register 0x2e */
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enum {
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HFLIP = BIT(7),
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VFLIP = BIT(6),
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DEPO_O = BIT(5),
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HPO_O = BIT(4),
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VPO_O = BIT(3),
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TE = GENMASK(2, 0),
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};
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/* Page 0, Register 0x2b */
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enum {
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SWAPS = GENMASK(7, 4),
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VFMT = GENMASK(3, 0),
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};
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/* Page 0, Register 0x54 */
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enum {
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COMP_BP = BIT(7),
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DAC_EN_T = BIT(6),
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HWO_HDMI_HI = GENMASK(5, 3),
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HOO_HDMI_HI = GENMASK(2, 0),
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};
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/* Page 0, Register 0x57 */
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enum {
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FLDSEN = BIT(7),
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VWO_HDMI_HI = GENMASK(5, 3),
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VOO_HDMI_HI = GENMASK(2, 0),
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};
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/* Page 0, Register 0x7e */
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enum {
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HDMI_LVDS_SEL = BIT(7),
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DE_GEN = BIT(6),
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PWM_INDEX_HI = BIT(5),
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USE_DE = BIT(4),
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R_INT = GENMASK(3, 0),
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};
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/* Page 1, Register 0x07 */
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enum {
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BPCKSEL = BIT(7),
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DRI_CMFB_EN = BIT(6),
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CEC_PUEN = BIT(5),
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CEC_T = BIT(3),
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CKINV = BIT(2),
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CK_TVINV = BIT(1),
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DRI_CKS2 = BIT(0),
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};
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/* Page 1, Register 0x08 */
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enum {
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DACG = BIT(6),
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DACKTST = BIT(5),
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DEDGEB = BIT(4),
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SYO = BIT(3),
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DRI_IT_LVDS = GENMASK(2, 1),
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DISPON = BIT(0),
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};
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/* Page 1, Register 0x0c */
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enum {
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DRI_PLL_CP = GENMASK(7, 6),
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DRI_PLL_DIVSEL = BIT(5),
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DRI_PLL_N1_1 = BIT(4),
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DRI_PLL_N1_0 = BIT(3),
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DRI_PLL_N3_1 = BIT(2),
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DRI_PLL_N3_0 = BIT(1),
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DRI_PLL_CKTSTEN = BIT(0),
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};
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/* Page 1, Register 0x6b */
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enum {
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VCO3CS = GENMASK(7, 6),
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ICPGBK2_0 = GENMASK(5, 3),
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DRI_VCO357SC = BIT(2),
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PDPLL2 = BIT(1),
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DRI_PD_SER = BIT(0),
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};
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/* Page 1, Register 0x6c */
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enum {
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PLL2N11 = GENMASK(7, 4),
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PLL2N5_4 = BIT(3),
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PLL2N5_TOP = BIT(2),
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DRI_PLL_PD = BIT(1),
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PD_I2CM = BIT(0),
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};
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/* Page 3, Register 0x28 */
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enum {
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DIFF_EN = GENMASK(7, 6),
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CORREC_EN = GENMASK(5, 4),
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VGACLK_BP = BIT(3),
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HM_LV_SEL = BIT(2),
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HD_VGA_SEL = BIT(1),
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};
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/* Page 3, Register 0x2a */
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enum {
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LVDSCLK_BP = BIT(7),
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HDTVCLK_BP = BIT(6),
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HDMICLK_BP = BIT(5),
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HDTV_BP = BIT(4),
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HDMI_BP = BIT(3),
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THRWL = GENMASK(2, 0),
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};
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/* Page 4, Register 0x52 */
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enum {
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PGM_ARSTB = BIT(7),
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MCU_ARSTB = BIT(6),
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MCU_RETB = BIT(2),
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RESETIB = BIT(1),
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RESETDB = BIT(0),
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};
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struct ch7033_priv {
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struct regmap *regmap;
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struct drm_bridge *next_bridge;
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struct drm_bridge bridge;
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struct drm_connector connector;
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};
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#define conn_to_ch7033_priv(x) \
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container_of(x, struct ch7033_priv, connector)
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#define bridge_to_ch7033_priv(x) \
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container_of(x, struct ch7033_priv, bridge)
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static enum drm_connector_status ch7033_connector_detect(
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struct drm_connector *connector, bool force)
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{
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struct ch7033_priv *priv = conn_to_ch7033_priv(connector);
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return drm_bridge_detect(priv->next_bridge);
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}
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static const struct drm_connector_funcs ch7033_connector_funcs = {
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.reset = drm_atomic_helper_connector_reset,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.detect = ch7033_connector_detect,
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.destroy = drm_connector_cleanup,
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.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
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};
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static int ch7033_connector_get_modes(struct drm_connector *connector)
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{
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struct ch7033_priv *priv = conn_to_ch7033_priv(connector);
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struct edid *edid;
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int ret;
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edid = drm_bridge_get_edid(priv->next_bridge, connector);
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drm_connector_update_edid_property(connector, edid);
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if (edid) {
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ret = drm_add_edid_modes(connector, edid);
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kfree(edid);
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} else {
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ret = drm_add_modes_noedid(connector, 1920, 1080);
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drm_set_preferred_mode(connector, 1024, 768);
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}
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return ret;
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}
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static struct drm_encoder *ch7033_connector_best_encoder(
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struct drm_connector *connector)
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{
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struct ch7033_priv *priv = conn_to_ch7033_priv(connector);
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return priv->bridge.encoder;
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}
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static const struct drm_connector_helper_funcs ch7033_connector_helper_funcs = {
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.get_modes = ch7033_connector_get_modes,
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.best_encoder = ch7033_connector_best_encoder,
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};
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static void ch7033_hpd_event(void *arg, enum drm_connector_status status)
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{
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struct ch7033_priv *priv = arg;
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if (priv->bridge.dev)
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drm_helper_hpd_irq_event(priv->connector.dev);
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}
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static int ch7033_bridge_attach(struct drm_bridge *bridge,
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enum drm_bridge_attach_flags flags)
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{
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struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
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struct drm_connector *connector = &priv->connector;
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int ret;
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ret = drm_bridge_attach(bridge->encoder, priv->next_bridge, bridge,
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DRM_BRIDGE_ATTACH_NO_CONNECTOR);
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if (ret)
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return ret;
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if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
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return 0;
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if (priv->next_bridge->ops & DRM_BRIDGE_OP_DETECT) {
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connector->polled = DRM_CONNECTOR_POLL_HPD;
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} else {
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connector->polled = DRM_CONNECTOR_POLL_CONNECT |
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DRM_CONNECTOR_POLL_DISCONNECT;
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}
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if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD) {
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drm_bridge_hpd_enable(priv->next_bridge, ch7033_hpd_event,
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priv);
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}
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drm_connector_helper_add(connector,
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&ch7033_connector_helper_funcs);
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ret = drm_connector_init_with_ddc(bridge->dev, &priv->connector,
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&ch7033_connector_funcs,
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priv->next_bridge->type,
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priv->next_bridge->ddc);
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if (ret) {
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DRM_ERROR("Failed to initialize connector\n");
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return ret;
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}
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return drm_connector_attach_encoder(&priv->connector, bridge->encoder);
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}
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static void ch7033_bridge_detach(struct drm_bridge *bridge)
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{
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struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
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if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD)
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drm_bridge_hpd_disable(priv->next_bridge);
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drm_connector_cleanup(&priv->connector);
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}
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static enum drm_mode_status ch7033_bridge_mode_valid(struct drm_bridge *bridge,
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const struct drm_display_info *info,
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const struct drm_display_mode *mode)
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{
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if (mode->clock > 165000)
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return MODE_CLOCK_HIGH;
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if (mode->hdisplay >= 1920)
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return MODE_BAD_HVALUE;
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if (mode->vdisplay >= 1080)
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return MODE_BAD_VVALUE;
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return MODE_OK;
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}
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static void ch7033_bridge_disable(struct drm_bridge *bridge)
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{
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struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
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regmap_write(priv->regmap, 0x03, 0x04);
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regmap_update_bits(priv->regmap, 0x52, RESETDB, 0x00);
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}
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static void ch7033_bridge_enable(struct drm_bridge *bridge)
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{
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struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
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regmap_write(priv->regmap, 0x03, 0x04);
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regmap_update_bits(priv->regmap, 0x52, RESETDB, RESETDB);
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}
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static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
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const struct drm_display_mode *mode,
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const struct drm_display_mode *adjusted_mode)
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{
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struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
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int hbporch = mode->hsync_start - mode->hdisplay;
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int hsynclen = mode->hsync_end - mode->hsync_start;
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int vbporch = mode->vsync_start - mode->vdisplay;
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int vsynclen = mode->vsync_end - mode->vsync_start;
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/*
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* Page 4
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*/
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regmap_write(priv->regmap, 0x03, 0x04);
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/* Turn everything off to set all the registers to their defaults. */
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regmap_write(priv->regmap, 0x52, 0x00);
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/* Bring I/O block up. */
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regmap_write(priv->regmap, 0x52, RESETIB);
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/*
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* Page 0
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*/
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regmap_write(priv->regmap, 0x03, 0x00);
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/* Bring up parts we need from the power down. */
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regmap_update_bits(priv->regmap, 0x07, DRI_PD | IO_PD, 0);
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|
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regmap_update_bits(priv->regmap, 0x08, DRI_PDDRI | PDDAC | PANEN, 0);
|
||
|
|
regmap_update_bits(priv->regmap, 0x09, DPD | GCKOFF |
|
||
|
|
HDMI_PD | VGA_PD, 0);
|
||
|
|
regmap_update_bits(priv->regmap, 0x0a, HD_DVIB, 0);
|
||
|
|
|
||
|
|
/* Horizontal input timing. */
|
||
|
|
regmap_write(priv->regmap, 0x0b, (mode->htotal >> 8) << 3 |
|
||
|
|
(mode->hdisplay >> 8));
|
||
|
|
regmap_write(priv->regmap, 0x0c, mode->hdisplay);
|
||
|
|
regmap_write(priv->regmap, 0x0d, mode->htotal);
|
||
|
|
regmap_write(priv->regmap, 0x0e, (hsynclen >> 8) << 3 |
|
||
|
|
(hbporch >> 8));
|
||
|
|
regmap_write(priv->regmap, 0x0f, hbporch);
|
||
|
|
regmap_write(priv->regmap, 0x10, hsynclen);
|
||
|
|
|
||
|
|
/* Vertical input timing. */
|
||
|
|
regmap_write(priv->regmap, 0x11, (mode->vtotal >> 8) << 3 |
|
||
|
|
(mode->vdisplay >> 8));
|
||
|
|
regmap_write(priv->regmap, 0x12, mode->vdisplay);
|
||
|
|
regmap_write(priv->regmap, 0x13, mode->vtotal);
|
||
|
|
regmap_write(priv->regmap, 0x14, ((vsynclen >> 8) << 3) |
|
||
|
|
(vbporch >> 8));
|
||
|
|
regmap_write(priv->regmap, 0x15, vbporch);
|
||
|
|
regmap_write(priv->regmap, 0x16, vsynclen);
|
||
|
|
|
||
|
|
/* Input color swap. */
|
||
|
|
regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
|
||
|
|
|
||
|
|
/* Input clock and sync polarity. */
|
||
|
|
regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16);
|
||
|
|
regmap_update_bits(priv->regmap, 0x19, HPO_I | VPO_I | GCLKFREQ,
|
||
|
|
(mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_I : 0 |
|
||
|
|
(mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_I : 0 |
|
||
|
|
mode->clock >> 16);
|
||
|
|
regmap_write(priv->regmap, 0x1a, mode->clock >> 8);
|
||
|
|
regmap_write(priv->regmap, 0x1b, mode->clock);
|
||
|
|
|
||
|
|
/* Horizontal output timing. */
|
||
|
|
regmap_write(priv->regmap, 0x1f, (mode->htotal >> 8) << 3 |
|
||
|
|
(mode->hdisplay >> 8));
|
||
|
|
regmap_write(priv->regmap, 0x20, mode->hdisplay);
|
||
|
|
regmap_write(priv->regmap, 0x21, mode->htotal);
|
||
|
|
|
||
|
|
/* Vertical output timing. */
|
||
|
|
regmap_write(priv->regmap, 0x25, (mode->vtotal >> 8) << 3 |
|
||
|
|
(mode->vdisplay >> 8));
|
||
|
|
regmap_write(priv->regmap, 0x26, mode->vdisplay);
|
||
|
|
regmap_write(priv->regmap, 0x27, mode->vtotal);
|
||
|
|
|
||
|
|
/* VGA channel bypass */
|
||
|
|
regmap_update_bits(priv->regmap, 0x2b, VFMT, 9);
|
||
|
|
|
||
|
|
/* Output sync polarity. */
|
||
|
|
regmap_update_bits(priv->regmap, 0x2e, HPO_O | VPO_O,
|
||
|
|
(mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_O : 0 |
|
||
|
|
(mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_O : 0);
|
||
|
|
|
||
|
|
/* HDMI horizontal output timing. */
|
||
|
|
regmap_update_bits(priv->regmap, 0x54, HWO_HDMI_HI | HOO_HDMI_HI,
|
||
|
|
(hsynclen >> 8) << 3 |
|
||
|
|
(hbporch >> 8));
|
||
|
|
regmap_write(priv->regmap, 0x55, hbporch);
|
||
|
|
regmap_write(priv->regmap, 0x56, hsynclen);
|
||
|
|
|
||
|
|
/* HDMI vertical output timing. */
|
||
|
|
regmap_update_bits(priv->regmap, 0x57, VWO_HDMI_HI | VOO_HDMI_HI,
|
||
|
|
(vsynclen >> 8) << 3 |
|
||
|
|
(vbporch >> 8));
|
||
|
|
regmap_write(priv->regmap, 0x58, vbporch);
|
||
|
|
regmap_write(priv->regmap, 0x59, vsynclen);
|
||
|
|
|
||
|
|
/* Pick HDMI, not LVDS. */
|
||
|
|
regmap_update_bits(priv->regmap, 0x7e, HDMI_LVDS_SEL, HDMI_LVDS_SEL);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Page 1
|
||
|
|
*/
|
||
|
|
regmap_write(priv->regmap, 0x03, 0x01);
|
||
|
|
|
||
|
|
/* No idea what these do, but VGA is wobbly and blinky without them. */
|
||
|
|
regmap_update_bits(priv->regmap, 0x07, CKINV, CKINV);
|
||
|
|
regmap_update_bits(priv->regmap, 0x08, DISPON, DISPON);
|
||
|
|
|
||
|
|
/* DRI PLL */
|
||
|
|
regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_DIVSEL, DRI_PLL_DIVSEL);
|
||
|
|
if (mode->clock <= 40000) {
|
||
|
|
regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 |
|
||
|
|
DRI_PLL_N1_0 |
|
||
|
|
DRI_PLL_N3_1 |
|
||
|
|
DRI_PLL_N3_0,
|
||
|
|
0);
|
||
|
|
} else if (mode->clock < 80000) {
|
||
|
|
regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 |
|
||
|
|
DRI_PLL_N1_0 |
|
||
|
|
DRI_PLL_N3_1 |
|
||
|
|
DRI_PLL_N3_0,
|
||
|
|
DRI_PLL_N3_0 |
|
||
|
|
DRI_PLL_N1_0);
|
||
|
|
} else {
|
||
|
|
regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 |
|
||
|
|
DRI_PLL_N1_0 |
|
||
|
|
DRI_PLL_N3_1 |
|
||
|
|
DRI_PLL_N3_0,
|
||
|
|
DRI_PLL_N3_1 |
|
||
|
|
DRI_PLL_N1_1);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* This seems to be color calibration for VGA. */
|
||
|
|
regmap_write(priv->regmap, 0x64, 0x29); /* LSB Blue */
|
||
|
|
regmap_write(priv->regmap, 0x65, 0x29); /* LSB Green */
|
||
|
|
regmap_write(priv->regmap, 0x66, 0x29); /* LSB Red */
|
||
|
|
regmap_write(priv->regmap, 0x67, 0x00); /* MSB Blue */
|
||
|
|
regmap_write(priv->regmap, 0x68, 0x00); /* MSB Green */
|
||
|
|
regmap_write(priv->regmap, 0x69, 0x00); /* MSB Red */
|
||
|
|
|
||
|
|
regmap_update_bits(priv->regmap, 0x6b, DRI_PD_SER, 0x00);
|
||
|
|
regmap_update_bits(priv->regmap, 0x6c, DRI_PLL_PD, 0x00);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Page 3
|
||
|
|
*/
|
||
|
|
regmap_write(priv->regmap, 0x03, 0x03);
|
||
|
|
|
||
|
|
/* More bypasses and apparently another HDMI/LVDS selector. */
|
||
|
|
regmap_update_bits(priv->regmap, 0x28, VGACLK_BP | HM_LV_SEL,
|
||
|
|
VGACLK_BP | HM_LV_SEL);
|
||
|
|
regmap_update_bits(priv->regmap, 0x2a, HDMICLK_BP | HDMI_BP,
|
||
|
|
HDMICLK_BP | HDMI_BP);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Page 4
|
||
|
|
*/
|
||
|
|
regmap_write(priv->regmap, 0x03, 0x04);
|
||
|
|
|
||
|
|
/* Output clock. */
|
||
|
|
regmap_write(priv->regmap, 0x10, mode->clock >> 16);
|
||
|
|
regmap_write(priv->regmap, 0x11, mode->clock >> 8);
|
||
|
|
regmap_write(priv->regmap, 0x12, mode->clock);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct drm_bridge_funcs ch7033_bridge_funcs = {
|
||
|
|
.attach = ch7033_bridge_attach,
|
||
|
|
.detach = ch7033_bridge_detach,
|
||
|
|
.mode_valid = ch7033_bridge_mode_valid,
|
||
|
|
.disable = ch7033_bridge_disable,
|
||
|
|
.enable = ch7033_bridge_enable,
|
||
|
|
.mode_set = ch7033_bridge_mode_set,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct regmap_config ch7033_regmap_config = {
|
||
|
|
.reg_bits = 8,
|
||
|
|
.val_bits = 8,
|
||
|
|
.max_register = 0x7f,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int ch7033_probe(struct i2c_client *client)
|
||
|
|
{
|
||
|
|
struct device *dev = &client->dev;
|
||
|
|
struct ch7033_priv *priv;
|
||
|
|
unsigned int val;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||
|
|
if (!priv)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
dev_set_drvdata(dev, priv);
|
||
|
|
|
||
|
|
ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1, NULL,
|
||
|
|
&priv->next_bridge);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
priv->regmap = devm_regmap_init_i2c(client, &ch7033_regmap_config);
|
||
|
|
if (IS_ERR(priv->regmap)) {
|
||
|
|
dev_err(&client->dev, "regmap init failed\n");
|
||
|
|
return PTR_ERR(priv->regmap);
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = regmap_read(priv->regmap, 0x00, &val);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(&client->dev, "error reading the model id: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
if ((val & 0xf7) != 0x56) {
|
||
|
|
dev_err(&client->dev, "the device is not a ch7033\n");
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
|
||
|
|
regmap_write(priv->regmap, 0x03, 0x04);
|
||
|
|
ret = regmap_read(priv->regmap, 0x51, &val);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(&client->dev, "error reading the model id: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
if ((val & 0x0f) != 3) {
|
||
|
|
dev_err(&client->dev, "unknown revision %u\n", val);
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
|
||
|
|
INIT_LIST_HEAD(&priv->bridge.list);
|
||
|
|
priv->bridge.funcs = &ch7033_bridge_funcs;
|
||
|
|
priv->bridge.of_node = dev->of_node;
|
||
|
|
drm_bridge_add(&priv->bridge);
|
||
|
|
|
||
|
|
dev_info(dev, "Chrontel CH7033 Video Encoder\n");
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void ch7033_remove(struct i2c_client *client)
|
||
|
|
{
|
||
|
|
struct device *dev = &client->dev;
|
||
|
|
struct ch7033_priv *priv = dev_get_drvdata(dev);
|
||
|
|
|
||
|
|
drm_bridge_remove(&priv->bridge);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id ch7033_dt_ids[] = {
|
||
|
|
{ .compatible = "chrontel,ch7033", },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, ch7033_dt_ids);
|
||
|
|
|
||
|
|
static const struct i2c_device_id ch7033_ids[] = {
|
||
|
|
{ "ch7033", 0 },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(i2c, ch7033_ids);
|
||
|
|
|
||
|
|
static struct i2c_driver ch7033_driver = {
|
||
|
|
.probe_new = ch7033_probe,
|
||
|
|
.remove = ch7033_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "ch7033",
|
||
|
|
.of_match_table = of_match_ptr(ch7033_dt_ids),
|
||
|
|
},
|
||
|
|
.id_table = ch7033_ids,
|
||
|
|
};
|
||
|
|
|
||
|
|
module_i2c_driver(ch7033_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
|
||
|
|
MODULE_DESCRIPTION("Chrontel CH7033 Video Encoder Driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|