122 lines
4.5 KiB
C
122 lines
4.5 KiB
C
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_BACKLIGHT_REGS_H__
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#define __INTEL_BACKLIGHT_REGS_H__
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#include "intel_display_reg_defs.h"
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#define _VLV_BLC_PWM_CTL2_A (VLV_DISPLAY_BASE + 0x61250)
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#define _VLV_BLC_PWM_CTL2_B (VLV_DISPLAY_BASE + 0x61350)
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#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, _VLV_BLC_PWM_CTL2_B)
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#define _VLV_BLC_PWM_CTL_A (VLV_DISPLAY_BASE + 0x61254)
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#define _VLV_BLC_PWM_CTL_B (VLV_DISPLAY_BASE + 0x61354)
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#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, _VLV_BLC_PWM_CTL_B)
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#define _VLV_BLC_HIST_CTL_A (VLV_DISPLAY_BASE + 0x61260)
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#define _VLV_BLC_HIST_CTL_B (VLV_DISPLAY_BASE + 0x61360)
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#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, _VLV_BLC_HIST_CTL_B)
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/* Backlight control */
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#define BLC_PWM_CTL2 _MMIO(0x61250) /* 965+ only */
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#define BLM_PWM_ENABLE (1 << 31)
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#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
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#define BLM_PIPE_SELECT (1 << 29)
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#define BLM_PIPE_SELECT_IVB (3 << 29)
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#define BLM_PIPE_A (0 << 29)
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#define BLM_PIPE_B (1 << 29)
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#define BLM_PIPE_C (2 << 29) /* ivb + */
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#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
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#define BLM_TRANSCODER_B BLM_PIPE_B
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#define BLM_TRANSCODER_C BLM_PIPE_C
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#define BLM_TRANSCODER_EDP (3 << 29)
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#define BLM_PIPE(pipe) ((pipe) << 29)
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#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
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#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
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#define BLM_PHASE_IN_ENABLE (1 << 25)
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#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
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#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
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#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
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#define BLM_PHASE_IN_COUNT_SHIFT (8)
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#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
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#define BLM_PHASE_IN_INCR_SHIFT (0)
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#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
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#define BLC_PWM_CTL _MMIO(0x61254)
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/*
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* This is the most significant 15 bits of the number of backlight cycles in a
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* complete cycle of the modulated backlight control.
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*
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* The actual value is this field multiplied by two.
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*/
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#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
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#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
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#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
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/*
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* This is the number of cycles out of the backlight modulation cycle for which
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* the backlight is on.
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*
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* This field must be no greater than the number of cycles in the complete
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* backlight modulation cycle.
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*/
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#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
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#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
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#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
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#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
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#define BLC_HIST_CTL _MMIO(0x61260)
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#define BLM_HISTOGRAM_ENABLE (1 << 31)
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/* New registers for PCH-split platforms. Safe where new bits show up, the
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* register layout machtes with gen4 BLC_PWM_CTL[12]. */
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#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
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#define BLC_PWM_CPU_CTL _MMIO(0x48254)
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#define HSW_BLC_PWM2_CTL _MMIO(0x48350)
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/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
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* like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
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#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
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#define BLM_PCH_PWM_ENABLE (1 << 31)
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#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
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#define BLM_PCH_POLARITY (1 << 29)
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#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
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/* BXT backlight register definition. */
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#define _BXT_BLC_PWM_CTL1 0xC8250
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#define BXT_BLC_PWM_ENABLE (1 << 31)
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#define BXT_BLC_PWM_POLARITY (1 << 29)
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#define _BXT_BLC_PWM_FREQ1 0xC8254
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#define _BXT_BLC_PWM_DUTY1 0xC8258
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#define _BXT_BLC_PWM_CTL2 0xC8350
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#define _BXT_BLC_PWM_FREQ2 0xC8354
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#define _BXT_BLC_PWM_DUTY2 0xC8358
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#define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
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_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
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#define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
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_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
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#define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
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_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
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/* Utility pin */
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#define UTIL_PIN_CTL _MMIO(0x48400)
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#define UTIL_PIN_ENABLE (1 << 31)
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#define UTIL_PIN_PIPE_MASK (3 << 29)
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#define UTIL_PIN_PIPE(x) ((x) << 29)
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#define UTIL_PIN_MODE_MASK (0xf << 24)
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#define UTIL_PIN_MODE_DATA (0 << 24)
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#define UTIL_PIN_MODE_PWM (1 << 24)
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#define UTIL_PIN_MODE_VBLANK (4 << 24)
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#define UTIL_PIN_MODE_VSYNC (5 << 24)
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#define UTIL_PIN_MODE_EYE_LEVEL (8 << 24)
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#define UTIL_PIN_OUTPUT_DATA (1 << 23)
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#define UTIL_PIN_POLARITY (1 << 22)
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#define UTIL_PIN_DIRECTION_INPUT (1 << 19)
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#define UTIL_PIN_INPUT_DATA (1 << 16)
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#endif /* __INTEL_BACKLIGHT_REGS_H__ */
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