181 lines
6.0 KiB
C
181 lines
6.0 KiB
C
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __I915_REG_DEFS__
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#define __I915_REG_DEFS__
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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/**
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* REG_BIT() - Prepare a u32 bit value
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* @__n: 0-based bit number
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*
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* Local wrapper for BIT() to force u32, with compile time checks.
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*
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* @return: Value with bit @__n set.
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*/
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#define REG_BIT(__n) \
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((u32)(BIT(__n) + \
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BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
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((__n) < 0 || (__n) > 31))))
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/**
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* REG_GENMASK() - Prepare a continuous u32 bitmask
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* @__high: 0-based high bit
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* @__low: 0-based low bit
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*
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* Local wrapper for GENMASK() to force u32, with compile time checks.
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*
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* @return: Continuous bitmask from @__high to @__low, inclusive.
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*/
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#define REG_GENMASK(__high, __low) \
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((u32)(GENMASK(__high, __low) + \
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BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
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__is_constexpr(__low) && \
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((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
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/**
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* REG_GENMASK64() - Prepare a continuous u64 bitmask
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* @__high: 0-based high bit
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* @__low: 0-based low bit
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*
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* Local wrapper for GENMASK_ULL() to force u64, with compile time checks.
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*
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* @return: Continuous bitmask from @__high to @__low, inclusive.
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*/
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#define REG_GENMASK64(__high, __low) \
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((u64)(GENMASK_ULL(__high, __low) + \
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BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
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__is_constexpr(__low) && \
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((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
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/*
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* Local integer constant expression version of is_power_of_2().
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*/
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#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
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/**
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* REG_FIELD_PREP() - Prepare a u32 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to put in the field
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*
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* Local copy of FIELD_PREP() to generate an integer constant expression, force
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* u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
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*
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* @return: @__val masked and shifted into the field defined by @__mask.
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*/
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#define REG_FIELD_PREP(__mask, __val) \
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((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
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BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
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BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
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BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
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BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
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/**
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* REG_FIELD_GET() - Extract a u32 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to extract the bitfield value from
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*
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* Local wrapper for FIELD_GET() to force u32 and for consistency with
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* REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
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*
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* @return: Masked and shifted value of the field defined by @__mask in @__val.
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*/
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#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
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/**
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* REG_FIELD_GET64() - Extract a u64 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to extract the bitfield value from
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*
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* Local wrapper for FIELD_GET() to force u64 and for consistency with
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* REG_GENMASK64().
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*
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* @return: Masked and shifted value of the field defined by @__mask in @__val.
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*/
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#define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val))
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#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
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#define _MASKED_FIELD(mask, value) ({ \
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if (__builtin_constant_p(mask)) \
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BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
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if (__builtin_constant_p(value)) \
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BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
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if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
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BUILD_BUG_ON_MSG((value) & ~(mask), \
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"Incorrect value for mask"); \
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__MASKED_FIELD(mask, value); })
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#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
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#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
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/*
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* Given the first two numbers __a and __b of arbitrarily many evenly spaced
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* numbers, pick the 0-based __index'th value.
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*
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* Always prefer this over _PICK() if the numbers are evenly spaced.
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*/
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#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
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/*
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* Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
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* @__c_index corresponds to the index in which the second range starts to be
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* used. Using math interval notation, the first range is used for indexes [ 0,
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* @__c_index), while the second range is used for [ @__c_index, ... ). Example:
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*
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* #define _FOO_A 0xf000
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* #define _FOO_B 0xf004
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* #define _FOO_C 0xf008
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* #define _SUPER_FOO_A 0xa000
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* #define _SUPER_FOO_B 0xa100
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* #define FOO(x) _MMIO(_PICK_EVEN_2RANGES(x, 3, \
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* _FOO_A, _FOO_B, \
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* _SUPER_FOO_A, _SUPER_FOO_B))
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*
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* This expands to:
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* 0: 0xf000,
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* 1: 0xf004,
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* 2: 0xf008,
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* 3: 0xa000,
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* 4: 0xa100,
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* 5: 0xa200,
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* ...
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*/
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#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d) \
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(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) + \
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((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) : \
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_PICK_EVEN((__index) - (__c_index), __c, __d)))
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/*
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* Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
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*
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* Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
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*/
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#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
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typedef struct {
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u32 reg;
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} i915_reg_t;
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#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
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typedef struct {
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u32 reg;
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} i915_mcr_reg_t;
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#define INVALID_MMIO_REG _MMIO(0)
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/*
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* These macros can be used on either i915_reg_t or i915_mcr_reg_t since they're
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* simply operations on the register's offset and don't care about the MCR vs
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* non-MCR nature of the register.
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*/
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#define i915_mmio_reg_offset(r) \
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_Generic((r), i915_reg_t: (r).reg, i915_mcr_reg_t: (r).reg)
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#define i915_mmio_reg_equal(a, b) (i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b))
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#define i915_mmio_reg_valid(r) (!i915_mmio_reg_equal(r, INVALID_MMIO_REG))
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#endif /* __I915_REG_DEFS__ */
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