119 lines
3.5 KiB
C
119 lines
3.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Linus Walleij <linus.walleij@linaro.org>
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* Parts of this file were based on the MCDE driver by Marcus Lorentzon
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* (C) ST-Ericsson SA 2013
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*/
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#include <drm/drm_simple_kms_helper.h>
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#ifndef _MCDE_DRM_H_
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#define _MCDE_DRM_H_
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/* Shared basic registers */
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#define MCDE_CR 0x00000000
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#define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_SHIFT 0
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#define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_MASK 0x0000003F
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#define MCDE_CR_IFIFOCTRLEN BIT(15)
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#define MCDE_CR_UFRECOVERY_MODE_V422 BIT(16)
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#define MCDE_CR_WRAP_MODE_V422_SHIFT BIT(17)
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#define MCDE_CR_AUTOCLKG_EN BIT(30)
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#define MCDE_CR_MCDEEN BIT(31)
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#define MCDE_CONF0 0x00000004
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#define MCDE_CONF0_SYNCMUX0 BIT(0)
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#define MCDE_CONF0_SYNCMUX1 BIT(1)
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#define MCDE_CONF0_SYNCMUX2 BIT(2)
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#define MCDE_CONF0_SYNCMUX3 BIT(3)
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#define MCDE_CONF0_SYNCMUX4 BIT(4)
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#define MCDE_CONF0_SYNCMUX5 BIT(5)
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#define MCDE_CONF0_SYNCMUX6 BIT(6)
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#define MCDE_CONF0_SYNCMUX7 BIT(7)
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#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12
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#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000
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#define MCDE_CONF0_OUTMUX0_SHIFT 16
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#define MCDE_CONF0_OUTMUX0_MASK 0x00070000
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#define MCDE_CONF0_OUTMUX1_SHIFT 19
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#define MCDE_CONF0_OUTMUX1_MASK 0x00380000
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#define MCDE_CONF0_OUTMUX2_SHIFT 22
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#define MCDE_CONF0_OUTMUX2_MASK 0x01C00000
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#define MCDE_CONF0_OUTMUX3_SHIFT 25
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#define MCDE_CONF0_OUTMUX3_MASK 0x0E000000
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#define MCDE_CONF0_OUTMUX4_SHIFT 28
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#define MCDE_CONF0_OUTMUX4_MASK 0x70000000
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#define MCDE_SSP 0x00000008
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#define MCDE_AIS 0x00000100
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#define MCDE_IMSCERR 0x00000110
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#define MCDE_RISERR 0x00000120
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#define MCDE_MISERR 0x00000130
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#define MCDE_SISERR 0x00000140
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enum mcde_flow_mode {
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/* One-shot mode: flow stops after one frame */
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MCDE_COMMAND_ONESHOT_FLOW,
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/* Command mode with tearing effect (TE) IRQ sync */
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MCDE_COMMAND_TE_FLOW,
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/*
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* Command mode with bus turn-around (BTA) and tearing effect
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* (TE) IRQ sync.
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*/
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MCDE_COMMAND_BTA_TE_FLOW,
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/* Video mode with tearing effect (TE) sync IRQ */
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MCDE_VIDEO_TE_FLOW,
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/* Video mode with the formatter itself as sync source */
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MCDE_VIDEO_FORMATTER_FLOW,
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/* DPI video with the formatter itsels as sync source */
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MCDE_DPI_FORMATTER_FLOW,
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};
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struct mcde {
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struct drm_device drm;
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struct device *dev;
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struct drm_panel *panel;
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struct drm_bridge *bridge;
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struct drm_connector *connector;
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struct drm_simple_display_pipe pipe;
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struct mipi_dsi_device *mdsi;
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bool dpi_output;
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s16 stride;
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enum mcde_flow_mode flow_mode;
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unsigned int flow_active;
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spinlock_t flow_lock; /* Locks the channel flow control */
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void __iomem *regs;
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struct clk *mcde_clk;
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struct clk *lcd_clk;
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struct clk *hdmi_clk;
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/* Handles to the clock dividers for FIFO A and B */
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struct clk *fifoa_clk;
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struct clk *fifob_clk;
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/* Locks the MCDE FIFO control register A and B */
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spinlock_t fifo_crx1_lock;
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struct regulator *epod;
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struct regulator *vana;
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};
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#define to_mcde(dev) container_of(dev, struct mcde, drm)
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static inline bool mcde_flow_is_video(struct mcde *mcde)
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{
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return (mcde->flow_mode == MCDE_VIDEO_TE_FLOW ||
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mcde->flow_mode == MCDE_VIDEO_FORMATTER_FLOW);
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}
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bool mcde_dsi_irq(struct mipi_dsi_device *mdsi);
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void mcde_dsi_te_request(struct mipi_dsi_device *mdsi);
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void mcde_dsi_enable(struct drm_bridge *bridge);
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void mcde_dsi_disable(struct drm_bridge *bridge);
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extern struct platform_driver mcde_dsi_driver;
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void mcde_display_irq(struct mcde *mcde);
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void mcde_display_disable_irqs(struct mcde *mcde);
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int mcde_display_init(struct drm_device *drm);
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int mcde_init_clock_divider(struct mcde *mcde);
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#endif /* _MCDE_DRM_H_ */
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