403 lines
11 KiB
C
403 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <linux/bitfield.h>
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#include <drm/drm_print.h>
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#include <drm/drm_fourcc.h>
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#include "meson_drv.h"
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#include "meson_registers.h"
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#include "meson_viu.h"
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#include "meson_rdma.h"
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#include "meson_osd_afbcd.h"
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/*
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* DOC: Driver for the ARM FrameBuffer Compression Decoders
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*
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* The Amlogic GXM and G12A SoC families embeds an AFBC Decoder,
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* to decode compressed buffers generated by the ARM Mali GPU.
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*
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* For the GXM Family, Amlogic designed their own Decoder, named in
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* the vendor source as "MESON_AFBC", and a single decoder is available
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* for the 2 OSD planes.
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* This decoder is compatible with the AFBC 1.0 specifications and the
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* Mali T820 GPU capabilities.
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* It supports :
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* - basic AFBC buffer for RGB32 only, thus YTR feature is mandatory
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* - SPARSE layout and SPLIT layout
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* - only 16x16 superblock
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*
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* The decoder reads the data from the SDRAM, decodes and sends the
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* decoded pixel stream to the OSD1 Plane pixel composer.
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*
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* For the G12A Family, Amlogic integrated an ARM AFBC Decoder, named
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* in the vendor source as "MALI_AFBC", and the decoder can decode up
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* to 4 surfaces, one for each of the 4 available OSDs.
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* This decoder is compatible with the AFBC 1.2 specifications for the
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* Mali G31 and G52 GPUs.
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* Is supports :
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* - basic AFBC buffer for multiple RGB and YUV pixel formats
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* - SPARSE layout and SPLIT layout
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* - 16x16 and 32x8 "wideblk" superblocks
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* - Tiled header
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*
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* The ARM AFBC Decoder independent from the VPU Pixel Pipeline, so
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* the ARM AFBC Decoder reads the data from the SDRAM then decodes
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* into a private internal physical address where the OSD1 Plane pixel
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* composer unpacks the decoded data.
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*/
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/* Amlogic AFBC Decoder for GXM Family */
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#define OSD1_AFBCD_RGB32 0x15
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static int meson_gxm_afbcd_pixel_fmt(u64 modifier, uint32_t format)
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{
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switch (format) {
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_ABGR8888:
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return OSD1_AFBCD_RGB32;
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/* TOFIX support mode formats */
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default:
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DRM_DEBUG("unsupported afbc format[%08x]\n", format);
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return -EINVAL;
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}
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}
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static bool meson_gxm_afbcd_supported_fmt(u64 modifier, uint32_t format)
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{
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if (modifier & AFBC_FORMAT_MOD_BLOCK_SIZE_32x8)
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return false;
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if (!(modifier & AFBC_FORMAT_MOD_YTR))
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return false;
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return meson_gxm_afbcd_pixel_fmt(modifier, format) >= 0;
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}
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static int meson_gxm_afbcd_reset(struct meson_drm *priv)
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{
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writel_relaxed(VIU_SW_RESET_OSD1_AFBCD,
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priv->io_base + _REG(VIU_SW_RESET));
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writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET));
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return 0;
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}
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static int meson_gxm_afbcd_init(struct meson_drm *priv)
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{
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return 0;
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}
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static void meson_gxm_afbcd_exit(struct meson_drm *priv)
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{
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meson_gxm_afbcd_reset(priv);
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}
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static int meson_gxm_afbcd_enable(struct meson_drm *priv)
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{
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writel_relaxed(FIELD_PREP(OSD1_AFBCD_ID_FIFO_THRD, 0x40) |
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OSD1_AFBCD_DEC_ENABLE,
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priv->io_base + _REG(OSD1_AFBCD_ENABLE));
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return 0;
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}
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static int meson_gxm_afbcd_disable(struct meson_drm *priv)
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{
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writel_bits_relaxed(OSD1_AFBCD_DEC_ENABLE, 0,
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priv->io_base + _REG(OSD1_AFBCD_ENABLE));
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return 0;
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}
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static int meson_gxm_afbcd_setup(struct meson_drm *priv)
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{
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u32 conv_lbuf_len;
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u32 mode = FIELD_PREP(OSD1_AFBCD_MIF_URGENT, 3) |
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FIELD_PREP(OSD1_AFBCD_HOLD_LINE_NUM, 4) |
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FIELD_PREP(OSD1_AFBCD_RGBA_EXCHAN_CTRL, 0x34) |
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meson_gxm_afbcd_pixel_fmt(priv->afbcd.modifier,
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priv->afbcd.format);
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if (priv->afbcd.modifier & AFBC_FORMAT_MOD_SPARSE)
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mode |= OSD1_AFBCD_HREG_HALF_BLOCK;
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if (priv->afbcd.modifier & AFBC_FORMAT_MOD_SPLIT)
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mode |= OSD1_AFBCD_HREG_BLOCK_SPLIT;
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writel_relaxed(mode, priv->io_base + _REG(OSD1_AFBCD_MODE));
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writel_relaxed(FIELD_PREP(OSD1_AFBCD_HREG_VSIZE_IN,
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priv->viu.osd1_width) |
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FIELD_PREP(OSD1_AFBCD_HREG_HSIZE_IN,
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priv->viu.osd1_height),
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priv->io_base + _REG(OSD1_AFBCD_SIZE_IN));
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writel_relaxed(priv->viu.osd1_addr >> 4,
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priv->io_base + _REG(OSD1_AFBCD_HDR_PTR));
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writel_relaxed(priv->viu.osd1_addr >> 4,
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priv->io_base + _REG(OSD1_AFBCD_FRAME_PTR));
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/* TOFIX: bits 31:24 are not documented, nor the meaning of 0xe4 */
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writel_relaxed((0xe4 << 24) | (priv->viu.osd1_addr & 0xffffff),
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priv->io_base + _REG(OSD1_AFBCD_CHROMA_PTR));
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if (priv->viu.osd1_width <= 128)
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conv_lbuf_len = 32;
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else if (priv->viu.osd1_width <= 256)
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conv_lbuf_len = 64;
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else if (priv->viu.osd1_width <= 512)
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conv_lbuf_len = 128;
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else if (priv->viu.osd1_width <= 1024)
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conv_lbuf_len = 256;
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else if (priv->viu.osd1_width <= 2048)
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conv_lbuf_len = 512;
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else
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conv_lbuf_len = 1024;
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writel_relaxed(conv_lbuf_len,
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priv->io_base + _REG(OSD1_AFBCD_CONV_CTRL));
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writel_relaxed(FIELD_PREP(OSD1_AFBCD_DEC_PIXEL_BGN_H, 0) |
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FIELD_PREP(OSD1_AFBCD_DEC_PIXEL_END_H,
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priv->viu.osd1_width - 1),
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priv->io_base + _REG(OSD1_AFBCD_PIXEL_HSCOPE));
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writel_relaxed(FIELD_PREP(OSD1_AFBCD_DEC_PIXEL_BGN_V, 0) |
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FIELD_PREP(OSD1_AFBCD_DEC_PIXEL_END_V,
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priv->viu.osd1_height - 1),
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priv->io_base + _REG(OSD1_AFBCD_PIXEL_VSCOPE));
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return 0;
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}
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struct meson_afbcd_ops meson_afbcd_gxm_ops = {
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.init = meson_gxm_afbcd_init,
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.exit = meson_gxm_afbcd_exit,
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.reset = meson_gxm_afbcd_reset,
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.enable = meson_gxm_afbcd_enable,
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.disable = meson_gxm_afbcd_disable,
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.setup = meson_gxm_afbcd_setup,
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.supported_fmt = meson_gxm_afbcd_supported_fmt,
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};
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/* ARM AFBC Decoder for G12A Family */
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/* Amlogic G12A Mali AFBC Decoder supported formats */
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enum {
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MAFBC_FMT_RGB565 = 0,
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MAFBC_FMT_RGBA5551,
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MAFBC_FMT_RGBA1010102,
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MAFBC_FMT_YUV420_10B,
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MAFBC_FMT_RGB888,
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MAFBC_FMT_RGBA8888,
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MAFBC_FMT_RGBA4444,
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MAFBC_FMT_R8,
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MAFBC_FMT_RG88,
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MAFBC_FMT_YUV420_8B,
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MAFBC_FMT_YUV422_8B = 11,
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MAFBC_FMT_YUV422_10B = 14,
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};
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static int meson_g12a_afbcd_pixel_fmt(u64 modifier, uint32_t format)
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{
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switch (format) {
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_ARGB8888:
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/* YTR is forbidden for non XBGR formats */
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if (modifier & AFBC_FORMAT_MOD_YTR)
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return -EINVAL;
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fallthrough;
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_ABGR8888:
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return MAFBC_FMT_RGBA8888;
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case DRM_FORMAT_RGB888:
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/* YTR is forbidden for non XBGR formats */
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if (modifier & AFBC_FORMAT_MOD_YTR)
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return -EINVAL;
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return MAFBC_FMT_RGB888;
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case DRM_FORMAT_RGB565:
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/* YTR is forbidden for non XBGR formats */
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if (modifier & AFBC_FORMAT_MOD_YTR)
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return -EINVAL;
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return MAFBC_FMT_RGB565;
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/* TOFIX support mode formats */
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default:
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DRM_DEBUG("unsupported afbc format[%08x]\n", format);
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return -EINVAL;
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}
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}
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static int meson_g12a_afbcd_bpp(uint32_t format)
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{
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switch (format) {
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_ABGR8888:
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return 32;
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case DRM_FORMAT_RGB888:
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return 24;
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case DRM_FORMAT_RGB565:
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return 16;
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/* TOFIX support mode formats */
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default:
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DRM_ERROR("unsupported afbc format[%08x]\n", format);
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return 0;
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}
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}
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static int meson_g12a_afbcd_fmt_to_blk_mode(u64 modifier, uint32_t format)
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{
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switch (format) {
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_ABGR8888:
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return OSD_MALI_COLOR_MODE_RGBA8888;
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case DRM_FORMAT_RGB888:
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return OSD_MALI_COLOR_MODE_RGB888;
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case DRM_FORMAT_RGB565:
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return OSD_MALI_COLOR_MODE_RGB565;
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/* TOFIX support mode formats */
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default:
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DRM_DEBUG("unsupported afbc format[%08x]\n", format);
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return -EINVAL;
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}
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}
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static bool meson_g12a_afbcd_supported_fmt(u64 modifier, uint32_t format)
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{
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return meson_g12a_afbcd_pixel_fmt(modifier, format) >= 0;
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}
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static int meson_g12a_afbcd_reset(struct meson_drm *priv)
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{
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meson_rdma_reset(priv);
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meson_rdma_writel_sync(priv, VIU_SW_RESET_G12A_AFBC_ARB |
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VIU_SW_RESET_G12A_OSD1_AFBCD,
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VIU_SW_RESET);
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meson_rdma_writel_sync(priv, 0, VIU_SW_RESET);
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return 0;
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}
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static int meson_g12a_afbcd_init(struct meson_drm *priv)
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{
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int ret;
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ret = meson_rdma_init(priv);
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if (ret)
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return ret;
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meson_rdma_setup(priv);
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/* Handle AFBC Decoder reset manually */
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writel_bits_relaxed(MALI_AFBCD_MANUAL_RESET, MALI_AFBCD_MANUAL_RESET,
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priv->io_base + _REG(MALI_AFBCD_TOP_CTRL));
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return 0;
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}
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static void meson_g12a_afbcd_exit(struct meson_drm *priv)
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{
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meson_g12a_afbcd_reset(priv);
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meson_rdma_free(priv);
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}
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static int meson_g12a_afbcd_enable(struct meson_drm *priv)
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{
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meson_rdma_writel_sync(priv, VPU_MAFBC_IRQ_SURFACES_COMPLETED |
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VPU_MAFBC_IRQ_CONFIGURATION_SWAPPED |
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VPU_MAFBC_IRQ_DECODE_ERROR |
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VPU_MAFBC_IRQ_DETILING_ERROR,
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VPU_MAFBC_IRQ_MASK);
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meson_rdma_writel_sync(priv, VPU_MAFBC_S0_ENABLE,
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VPU_MAFBC_SURFACE_CFG);
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meson_rdma_writel_sync(priv, VPU_MAFBC_DIRECT_SWAP,
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VPU_MAFBC_COMMAND);
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/* This will enable the RDMA replaying the register writes on vsync */
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meson_rdma_flush(priv);
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return 0;
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}
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static int meson_g12a_afbcd_disable(struct meson_drm *priv)
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{
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writel_bits_relaxed(VPU_MAFBC_S0_ENABLE, 0,
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priv->io_base + _REG(VPU_MAFBC_SURFACE_CFG));
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return 0;
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}
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static int meson_g12a_afbcd_setup(struct meson_drm *priv)
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{
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u32 format = meson_g12a_afbcd_pixel_fmt(priv->afbcd.modifier,
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priv->afbcd.format);
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|
|
if (priv->afbcd.modifier & AFBC_FORMAT_MOD_YTR)
|
||
|
|
format |= VPU_MAFBC_YUV_TRANSFORM;
|
||
|
|
|
||
|
|
if (priv->afbcd.modifier & AFBC_FORMAT_MOD_SPLIT)
|
||
|
|
format |= VPU_MAFBC_BLOCK_SPLIT;
|
||
|
|
|
||
|
|
if (priv->afbcd.modifier & AFBC_FORMAT_MOD_TILED)
|
||
|
|
format |= VPU_MAFBC_TILED_HEADER_EN;
|
||
|
|
|
||
|
|
if ((priv->afbcd.modifier & AFBC_FORMAT_MOD_BLOCK_SIZE_MASK) ==
|
||
|
|
AFBC_FORMAT_MOD_BLOCK_SIZE_32x8)
|
||
|
|
format |= FIELD_PREP(VPU_MAFBC_SUPER_BLOCK_ASPECT, 1);
|
||
|
|
|
||
|
|
meson_rdma_writel_sync(priv, format,
|
||
|
|
VPU_MAFBC_FORMAT_SPECIFIER_S0);
|
||
|
|
|
||
|
|
meson_rdma_writel_sync(priv, priv->viu.osd1_addr,
|
||
|
|
VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0);
|
||
|
|
meson_rdma_writel_sync(priv, 0,
|
||
|
|
VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0);
|
||
|
|
|
||
|
|
meson_rdma_writel_sync(priv, priv->viu.osd1_width,
|
||
|
|
VPU_MAFBC_BUFFER_WIDTH_S0);
|
||
|
|
meson_rdma_writel_sync(priv, ALIGN(priv->viu.osd1_height, 32),
|
||
|
|
VPU_MAFBC_BUFFER_HEIGHT_S0);
|
||
|
|
|
||
|
|
meson_rdma_writel_sync(priv, 0,
|
||
|
|
VPU_MAFBC_BOUNDING_BOX_X_START_S0);
|
||
|
|
meson_rdma_writel_sync(priv, priv->viu.osd1_width - 1,
|
||
|
|
VPU_MAFBC_BOUNDING_BOX_X_END_S0);
|
||
|
|
meson_rdma_writel_sync(priv, 0,
|
||
|
|
VPU_MAFBC_BOUNDING_BOX_Y_START_S0);
|
||
|
|
meson_rdma_writel_sync(priv, priv->viu.osd1_height - 1,
|
||
|
|
VPU_MAFBC_BOUNDING_BOX_Y_END_S0);
|
||
|
|
|
||
|
|
meson_rdma_writel_sync(priv, MESON_G12A_AFBCD_OUT_ADDR,
|
||
|
|
VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0);
|
||
|
|
meson_rdma_writel_sync(priv, 0,
|
||
|
|
VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0);
|
||
|
|
|
||
|
|
meson_rdma_writel_sync(priv, priv->viu.osd1_width *
|
||
|
|
(meson_g12a_afbcd_bpp(priv->afbcd.format) / 8),
|
||
|
|
VPU_MAFBC_OUTPUT_BUF_STRIDE_S0);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
struct meson_afbcd_ops meson_afbcd_g12a_ops = {
|
||
|
|
.init = meson_g12a_afbcd_init,
|
||
|
|
.exit = meson_g12a_afbcd_exit,
|
||
|
|
.reset = meson_g12a_afbcd_reset,
|
||
|
|
.enable = meson_g12a_afbcd_enable,
|
||
|
|
.disable = meson_g12a_afbcd_disable,
|
||
|
|
.setup = meson_g12a_afbcd_setup,
|
||
|
|
.fmt_to_blk_mode = meson_g12a_afbcd_fmt_to_blk_mode,
|
||
|
|
.supported_fmt = meson_g12a_afbcd_supported_fmt,
|
||
|
|
};
|