391 lines
11 KiB
C
391 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2016 The Linux Foundation. All rights reserved.
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*/
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#include <linux/pm_opp.h>
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#include "a5xx_gpu.h"
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/*
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* The GPMU data block is a block of shared registers that can be used to
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* communicate back and forth. These "registers" are by convention with the GPMU
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* firwmare and not bound to any specific hardware design
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*/
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#define AGC_INIT_BASE REG_A5XX_GPMU_DATA_RAM_BASE
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#define AGC_INIT_MSG_MAGIC (AGC_INIT_BASE + 5)
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#define AGC_MSG_BASE (AGC_INIT_BASE + 7)
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#define AGC_MSG_STATE (AGC_MSG_BASE + 0)
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#define AGC_MSG_COMMAND (AGC_MSG_BASE + 1)
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#define AGC_MSG_PAYLOAD_SIZE (AGC_MSG_BASE + 3)
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#define AGC_MSG_PAYLOAD(_o) ((AGC_MSG_BASE + 5) + (_o))
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#define AGC_POWER_CONFIG_PRODUCTION_ID 1
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#define AGC_INIT_MSG_VALUE 0xBABEFACE
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/* AGC_LM_CONFIG (A540+) */
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#define AGC_LM_CONFIG (136/4)
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#define AGC_LM_CONFIG_GPU_VERSION_SHIFT 17
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#define AGC_LM_CONFIG_ENABLE_GPMU_ADAPTIVE 1
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#define AGC_LM_CONFIG_THROTTLE_DISABLE (2 << 8)
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#define AGC_LM_CONFIG_ISENSE_ENABLE (1 << 4)
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#define AGC_LM_CONFIG_ENABLE_ERROR (3 << 4)
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#define AGC_LM_CONFIG_LLM_ENABLED (1 << 16)
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#define AGC_LM_CONFIG_BCL_DISABLED (1 << 24)
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#define AGC_LEVEL_CONFIG (140/4)
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static struct {
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uint32_t reg;
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uint32_t value;
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} a5xx_sequence_regs[] = {
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{ 0xB9A1, 0x00010303 },
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{ 0xB9A2, 0x13000000 },
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{ 0xB9A3, 0x00460020 },
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{ 0xB9A4, 0x10000000 },
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{ 0xB9A5, 0x040A1707 },
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{ 0xB9A6, 0x00010000 },
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{ 0xB9A7, 0x0E000904 },
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{ 0xB9A8, 0x10000000 },
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{ 0xB9A9, 0x01165000 },
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{ 0xB9AA, 0x000E0002 },
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{ 0xB9AB, 0x03884141 },
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{ 0xB9AC, 0x10000840 },
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{ 0xB9AD, 0x572A5000 },
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{ 0xB9AE, 0x00000003 },
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{ 0xB9AF, 0x00000000 },
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{ 0xB9B0, 0x10000000 },
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{ 0xB828, 0x6C204010 },
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{ 0xB829, 0x6C204011 },
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{ 0xB82A, 0x6C204012 },
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{ 0xB82B, 0x6C204013 },
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{ 0xB82C, 0x6C204014 },
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{ 0xB90F, 0x00000004 },
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{ 0xB910, 0x00000002 },
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{ 0xB911, 0x00000002 },
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{ 0xB912, 0x00000002 },
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{ 0xB913, 0x00000002 },
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{ 0xB92F, 0x00000004 },
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{ 0xB930, 0x00000005 },
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{ 0xB931, 0x00000005 },
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{ 0xB932, 0x00000005 },
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{ 0xB933, 0x00000005 },
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{ 0xB96F, 0x00000001 },
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{ 0xB970, 0x00000003 },
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{ 0xB94F, 0x00000004 },
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{ 0xB950, 0x0000000B },
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{ 0xB951, 0x0000000B },
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{ 0xB952, 0x0000000B },
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{ 0xB953, 0x0000000B },
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{ 0xB907, 0x00000019 },
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{ 0xB927, 0x00000019 },
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{ 0xB947, 0x00000019 },
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{ 0xB967, 0x00000019 },
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{ 0xB987, 0x00000019 },
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{ 0xB906, 0x00220001 },
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{ 0xB926, 0x00220001 },
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{ 0xB946, 0x00220001 },
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{ 0xB966, 0x00220001 },
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{ 0xB986, 0x00300000 },
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{ 0xAC40, 0x0340FF41 },
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{ 0xAC41, 0x03BEFED0 },
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{ 0xAC42, 0x00331FED },
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{ 0xAC43, 0x021FFDD3 },
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{ 0xAC44, 0x5555AAAA },
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{ 0xAC45, 0x5555AAAA },
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{ 0xB9BA, 0x00000008 },
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};
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/*
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* Get the actual voltage value for the operating point at the specified
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* frequency
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*/
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static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq)
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{
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struct drm_device *dev = gpu->dev;
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struct msm_drm_private *priv = dev->dev_private;
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struct platform_device *pdev = priv->gpu_pdev;
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struct dev_pm_opp *opp;
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u32 ret = 0;
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opp = dev_pm_opp_find_freq_exact(&pdev->dev, freq, true);
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if (!IS_ERR(opp)) {
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ret = dev_pm_opp_get_voltage(opp) / 1000;
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dev_pm_opp_put(opp);
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}
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return ret;
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}
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/* Setup thermal limit management */
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static void a530_lm_setup(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
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unsigned int i;
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/* Write the block of sequence registers */
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for (i = 0; i < ARRAY_SIZE(a5xx_sequence_regs); i++)
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gpu_write(gpu, a5xx_sequence_regs[i].reg,
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a5xx_sequence_regs[i].value);
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/* Hard code the A530 GPU thermal sensor ID for the GPMU */
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gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007);
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gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01);
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gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01);
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/* Until we get clock scaling 0 is always the active power level */
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gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0);
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gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAGE, a5xx_gpu->lm_leakage);
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/* The threshold is fixed at 6000 for A530 */
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gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000);
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gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF);
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gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x00201FF1);
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/* Write the voltage table */
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gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF);
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gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x201FF1);
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gpu_write(gpu, AGC_MSG_STATE, 1);
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gpu_write(gpu, AGC_MSG_COMMAND, AGC_POWER_CONFIG_PRODUCTION_ID);
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/* Write the max power - hard coded to 5448 for A530 */
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gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448);
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gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1);
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/*
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* For now just write the one voltage level - we will do more when we
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* can do scaling
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*/
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gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate));
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gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000);
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gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE, 4 * sizeof(uint32_t));
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gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE);
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}
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#define PAYLOAD_SIZE(_size) ((_size) * sizeof(u32))
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#define LM_DCVS_LIMIT 1
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#define LEVEL_CONFIG ~(0x303)
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static void a540_lm_setup(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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u32 config;
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/* The battery current limiter isn't enabled for A540 */
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config = AGC_LM_CONFIG_BCL_DISABLED;
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config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
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/* For now disable GPMU side throttling */
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config |= AGC_LM_CONFIG_THROTTLE_DISABLE;
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/* Until we get clock scaling 0 is always the active power level */
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gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0);
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/* Fixed at 6000 for now */
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gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000);
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gpu_write(gpu, AGC_MSG_STATE, 0x80000001);
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gpu_write(gpu, AGC_MSG_COMMAND, AGC_POWER_CONFIG_PRODUCTION_ID);
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gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448);
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gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1);
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gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate));
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gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000);
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gpu_write(gpu, AGC_MSG_PAYLOAD(AGC_LM_CONFIG), config);
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gpu_write(gpu, AGC_MSG_PAYLOAD(AGC_LEVEL_CONFIG), LEVEL_CONFIG);
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gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE,
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PAYLOAD_SIZE(AGC_LEVEL_CONFIG + 1));
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gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE);
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}
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/* Enable SP/TP cpower collapse */
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static void a5xx_pc_init(struct msm_gpu *gpu)
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{
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gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL, 0x7F);
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gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_BINNING_CTRL, 0);
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gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST, 0xA0080);
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gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY, 0x600040);
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}
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/* Enable the GPMU microcontroller */
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static int a5xx_gpmu_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
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struct msm_ringbuffer *ring = gpu->rb[0];
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if (!a5xx_gpu->gpmu_dwords)
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return 0;
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/* Turn off protected mode for this operation */
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OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
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OUT_RING(ring, 0);
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/* Kick off the IB to load the GPMU microcode */
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OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);
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OUT_RING(ring, lower_32_bits(a5xx_gpu->gpmu_iova));
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OUT_RING(ring, upper_32_bits(a5xx_gpu->gpmu_iova));
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OUT_RING(ring, a5xx_gpu->gpmu_dwords);
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/* Turn back on protected mode */
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OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
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OUT_RING(ring, 1);
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a5xx_flush(gpu, ring, true);
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if (!a5xx_idle(gpu, ring)) {
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DRM_ERROR("%s: Unable to load GPMU firmware. GPMU will not be active\n",
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gpu->name);
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return -EINVAL;
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}
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if (adreno_is_a530(adreno_gpu))
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gpu_write(gpu, REG_A5XX_GPMU_WFI_CONFIG, 0x4014);
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/* Kick off the GPMU */
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gpu_write(gpu, REG_A5XX_GPMU_CM3_SYSRESET, 0x0);
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/*
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* Wait for the GPMU to respond. It isn't fatal if it doesn't, we just
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* won't have advanced power collapse.
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*/
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if (spin_usecs(gpu, 25, REG_A5XX_GPMU_GENERAL_0, 0xFFFFFFFF,
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0xBABEFACE))
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DRM_ERROR("%s: GPMU firmware initialization timed out\n",
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gpu->name);
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if (!adreno_is_a530(adreno_gpu)) {
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u32 val = gpu_read(gpu, REG_A5XX_GPMU_GENERAL_1);
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if (val)
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DRM_ERROR("%s: GPMU firmware initialization failed: %d\n",
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gpu->name, val);
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}
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return 0;
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}
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/* Enable limits management */
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static void a5xx_lm_enable(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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/* This init sequence only applies to A530 */
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if (!adreno_is_a530(adreno_gpu))
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return;
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gpu_write(gpu, REG_A5XX_GDPM_INT_MASK, 0x0);
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gpu_write(gpu, REG_A5XX_GDPM_INT_EN, 0x0A);
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gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK, 0x01);
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gpu_write(gpu, REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK, 0x50000);
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gpu_write(gpu, REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL, 0x30000);
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gpu_write(gpu, REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL, 0x011);
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}
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int a5xx_power_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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int ret;
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/* Not all A5xx chips have a GPMU */
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if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu)))
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return 0;
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/* Set up the limits management */
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if (adreno_is_a530(adreno_gpu))
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a530_lm_setup(gpu);
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else if (adreno_is_a540(adreno_gpu))
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a540_lm_setup(gpu);
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/* Set up SP/TP power collpase */
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a5xx_pc_init(gpu);
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/* Start the GPMU */
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ret = a5xx_gpmu_init(gpu);
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if (ret)
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return ret;
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/* Start the limits management */
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a5xx_lm_enable(gpu);
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return 0;
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}
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void a5xx_gpmu_ucode_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||
|
|
struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
|
||
|
|
struct drm_device *drm = gpu->dev;
|
||
|
|
uint32_t dwords = 0, offset = 0, bosize;
|
||
|
|
unsigned int *data, *ptr, *cmds;
|
||
|
|
unsigned int cmds_size;
|
||
|
|
|
||
|
|
if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu)))
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (a5xx_gpu->gpmu_bo)
|
||
|
|
return;
|
||
|
|
|
||
|
|
data = (unsigned int *) adreno_gpu->fw[ADRENO_FW_GPMU]->data;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The first dword is the size of the remaining data in dwords. Use it
|
||
|
|
* as a checksum of sorts and make sure it matches the actual size of
|
||
|
|
* the firmware that we read
|
||
|
|
*/
|
||
|
|
|
||
|
|
if (adreno_gpu->fw[ADRENO_FW_GPMU]->size < 8 ||
|
||
|
|
(data[0] < 2) || (data[0] >=
|
||
|
|
(adreno_gpu->fw[ADRENO_FW_GPMU]->size >> 2)))
|
||
|
|
return;
|
||
|
|
|
||
|
|
/* The second dword is an ID - look for 2 (GPMU_FIRMWARE_ID) */
|
||
|
|
if (data[1] != 2)
|
||
|
|
return;
|
||
|
|
|
||
|
|
cmds = data + data[2] + 3;
|
||
|
|
cmds_size = data[0] - data[2] - 2;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* A single type4 opcode can only have so many values attached so
|
||
|
|
* add enough opcodes to load the all the commands
|
||
|
|
*/
|
||
|
|
bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2;
|
||
|
|
|
||
|
|
ptr = msm_gem_kernel_new(drm, bosize,
|
||
|
|
MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace,
|
||
|
|
&a5xx_gpu->gpmu_bo, &a5xx_gpu->gpmu_iova);
|
||
|
|
if (IS_ERR(ptr))
|
||
|
|
return;
|
||
|
|
|
||
|
|
msm_gem_object_set_name(a5xx_gpu->gpmu_bo, "gpmufw");
|
||
|
|
|
||
|
|
while (cmds_size > 0) {
|
||
|
|
int i;
|
||
|
|
uint32_t _size = cmds_size > TYPE4_MAX_PAYLOAD ?
|
||
|
|
TYPE4_MAX_PAYLOAD : cmds_size;
|
||
|
|
|
||
|
|
ptr[dwords++] = PKT4(REG_A5XX_GPMU_INST_RAM_BASE + offset,
|
||
|
|
_size);
|
||
|
|
|
||
|
|
for (i = 0; i < _size; i++)
|
||
|
|
ptr[dwords++] = *cmds++;
|
||
|
|
|
||
|
|
offset += _size;
|
||
|
|
cmds_size -= _size;
|
||
|
|
}
|
||
|
|
|
||
|
|
msm_gem_put_vaddr(a5xx_gpu->gpmu_bo);
|
||
|
|
a5xx_gpu->gpmu_dwords = dwords;
|
||
|
|
}
|