446 lines
14 KiB
C
446 lines
14 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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* Author: Vinay Simha <vinaysimha@inforcecomputing.com>
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*/
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#include <linux/delay.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_probe_helper.h>
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#include "mdp4_kms.h"
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struct mdp4_lcdc_encoder {
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struct drm_encoder base;
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struct device_node *panel_node;
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struct drm_panel *panel;
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struct clk *lcdc_clk;
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unsigned long int pixclock;
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struct regulator *regs[3];
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bool enabled;
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uint32_t bsc;
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};
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#define to_mdp4_lcdc_encoder(x) container_of(x, struct mdp4_lcdc_encoder, base)
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static struct mdp4_kms *get_kms(struct drm_encoder *encoder)
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{
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struct msm_drm_private *priv = encoder->dev->dev_private;
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return to_mdp4_kms(to_mdp_kms(priv->kms));
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}
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static void mdp4_lcdc_encoder_destroy(struct drm_encoder *encoder)
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{
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struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
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to_mdp4_lcdc_encoder(encoder);
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drm_encoder_cleanup(encoder);
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kfree(mdp4_lcdc_encoder);
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}
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static const struct drm_encoder_funcs mdp4_lcdc_encoder_funcs = {
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.destroy = mdp4_lcdc_encoder_destroy,
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};
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/* this should probably be a helper: */
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static struct drm_connector *get_connector(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_connector *connector;
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list_for_each_entry(connector, &dev->mode_config.connector_list, head)
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if (connector->encoder == encoder)
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return connector;
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return NULL;
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}
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static void setup_phy(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_connector *connector = get_connector(encoder);
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struct mdp4_kms *mdp4_kms = get_kms(encoder);
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uint32_t lvds_intf = 0, lvds_phy_cfg0 = 0;
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int bpp, nchan, swap;
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if (!connector)
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return;
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bpp = 3 * connector->display_info.bpc;
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if (!bpp)
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bpp = 18;
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/* TODO, these should come from panel somehow: */
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nchan = 1;
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swap = 0;
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switch (bpp) {
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case 24:
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0),
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x08) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x05) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x04) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x03));
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0),
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x02) |
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x01) |
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x00));
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1),
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x11) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x10) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x0d) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x0c));
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1),
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x0b) |
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x0a) |
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x09));
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2),
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x1a) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x19) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x18) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x15));
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2),
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x14) |
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x13) |
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x12));
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(3),
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x1b) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x17) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x16) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x0f));
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(3),
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x0e) |
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x07) |
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x06));
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if (nchan == 2) {
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lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN;
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} else {
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lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN;
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}
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break;
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case 18:
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0),
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x0a) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x07) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x06) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x05));
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0),
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x04) |
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x03) |
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x02));
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1),
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x13) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x12) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x0f) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x0e));
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1),
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x0d) |
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x0c) |
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x0b));
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2),
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x1a) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x19) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x18) |
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MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x17));
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2),
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x16) |
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x15) |
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MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x14));
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if (nchan == 2) {
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lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN;
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} else {
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lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN;
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}
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lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT;
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break;
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default:
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DRM_DEV_ERROR(dev->dev, "unknown bpp: %d\n", bpp);
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return;
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}
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switch (nchan) {
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case 1:
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lvds_phy_cfg0 = MDP4_LVDS_PHY_CFG0_CHANNEL0;
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lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN |
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MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL;
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break;
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case 2:
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lvds_phy_cfg0 = MDP4_LVDS_PHY_CFG0_CHANNEL0 |
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MDP4_LVDS_PHY_CFG0_CHANNEL1;
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lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN |
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MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN;
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break;
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default:
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DRM_DEV_ERROR(dev->dev, "unknown # of channels: %d\n", nchan);
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return;
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}
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if (swap)
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lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP;
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lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_ENABLE;
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mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, lvds_phy_cfg0);
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_INTF_CTL, lvds_intf);
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mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG2, 0x30);
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mb();
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udelay(1);
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lvds_phy_cfg0 |= MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE;
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mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, lvds_phy_cfg0);
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}
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static void mdp4_lcdc_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
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to_mdp4_lcdc_encoder(encoder);
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struct mdp4_kms *mdp4_kms = get_kms(encoder);
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uint32_t lcdc_hsync_skew, vsync_period, vsync_len, ctrl_pol;
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uint32_t display_v_start, display_v_end;
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uint32_t hsync_start_x, hsync_end_x;
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mode = adjusted_mode;
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DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode));
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mdp4_lcdc_encoder->pixclock = mode->clock * 1000;
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DBG("pixclock=%lu", mdp4_lcdc_encoder->pixclock);
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ctrl_pol = 0;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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ctrl_pol |= MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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ctrl_pol |= MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW;
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/* probably need to get DATA_EN polarity from panel.. */
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lcdc_hsync_skew = 0; /* get this from panel? */
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hsync_start_x = (mode->htotal - mode->hsync_start);
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hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
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vsync_period = mode->vtotal * mode->htotal;
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vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
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display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + lcdc_hsync_skew;
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display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + lcdc_hsync_skew - 1;
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_HSYNC_CTRL,
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MDP4_LCDC_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) |
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MDP4_LCDC_HSYNC_CTRL_PERIOD(mode->htotal));
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_VSYNC_PERIOD, vsync_period);
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_VSYNC_LEN, vsync_len);
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_HCTRL,
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MDP4_LCDC_DISPLAY_HCTRL_START(hsync_start_x) |
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MDP4_LCDC_DISPLAY_HCTRL_END(hsync_end_x));
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VSTART, display_v_start);
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VEND, display_v_end);
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_BORDER_CLR, 0);
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mdp4_write(mdp4_kms, REG_MDP4_LCDC_UNDERFLOW_CLR,
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MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY |
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MDP4_LCDC_UNDERFLOW_CLR_COLOR(0xff));
|
||
|
|
mdp4_write(mdp4_kms, REG_MDP4_LCDC_HSYNC_SKEW, lcdc_hsync_skew);
|
||
|
|
mdp4_write(mdp4_kms, REG_MDP4_LCDC_CTRL_POLARITY, ctrl_pol);
|
||
|
|
mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_HCTL,
|
||
|
|
MDP4_LCDC_ACTIVE_HCTL_START(0) |
|
||
|
|
MDP4_LCDC_ACTIVE_HCTL_END(0));
|
||
|
|
mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_VSTART, 0);
|
||
|
|
mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_VEND, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void mdp4_lcdc_encoder_disable(struct drm_encoder *encoder)
|
||
|
|
{
|
||
|
|
struct drm_device *dev = encoder->dev;
|
||
|
|
struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
|
||
|
|
to_mdp4_lcdc_encoder(encoder);
|
||
|
|
struct mdp4_kms *mdp4_kms = get_kms(encoder);
|
||
|
|
struct drm_panel *panel;
|
||
|
|
int i, ret;
|
||
|
|
|
||
|
|
if (WARN_ON(!mdp4_lcdc_encoder->enabled))
|
||
|
|
return;
|
||
|
|
|
||
|
|
mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
|
||
|
|
|
||
|
|
panel = of_drm_find_panel(mdp4_lcdc_encoder->panel_node);
|
||
|
|
if (!IS_ERR(panel)) {
|
||
|
|
drm_panel_disable(panel);
|
||
|
|
drm_panel_unprepare(panel);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Wait for a vsync so we know the ENABLE=0 latched before
|
||
|
|
* the (connector) source of the vsync's gets disabled,
|
||
|
|
* otherwise we end up in a funny state if we re-enable
|
||
|
|
* before the disable latches, which results that some of
|
||
|
|
* the settings changes for the new modeset (like new
|
||
|
|
* scanout buffer) don't latch properly..
|
||
|
|
*/
|
||
|
|
mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_PRIMARY_VSYNC);
|
||
|
|
|
||
|
|
clk_disable_unprepare(mdp4_lcdc_encoder->lcdc_clk);
|
||
|
|
|
||
|
|
for (i = 0; i < ARRAY_SIZE(mdp4_lcdc_encoder->regs); i++) {
|
||
|
|
ret = regulator_disable(mdp4_lcdc_encoder->regs[i]);
|
||
|
|
if (ret)
|
||
|
|
DRM_DEV_ERROR(dev->dev, "failed to disable regulator: %d\n", ret);
|
||
|
|
}
|
||
|
|
|
||
|
|
mdp4_lcdc_encoder->enabled = false;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void mdp4_lcdc_encoder_enable(struct drm_encoder *encoder)
|
||
|
|
{
|
||
|
|
struct drm_device *dev = encoder->dev;
|
||
|
|
struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
|
||
|
|
to_mdp4_lcdc_encoder(encoder);
|
||
|
|
unsigned long pc = mdp4_lcdc_encoder->pixclock;
|
||
|
|
struct mdp4_kms *mdp4_kms = get_kms(encoder);
|
||
|
|
struct drm_panel *panel;
|
||
|
|
uint32_t config;
|
||
|
|
int i, ret;
|
||
|
|
|
||
|
|
if (WARN_ON(mdp4_lcdc_encoder->enabled))
|
||
|
|
return;
|
||
|
|
|
||
|
|
/* TODO: hard-coded for 18bpp: */
|
||
|
|
config =
|
||
|
|
MDP4_DMA_CONFIG_R_BPC(BPC6) |
|
||
|
|
MDP4_DMA_CONFIG_G_BPC(BPC6) |
|
||
|
|
MDP4_DMA_CONFIG_B_BPC(BPC6) |
|
||
|
|
MDP4_DMA_CONFIG_PACK(0x21) |
|
||
|
|
MDP4_DMA_CONFIG_DEFLKR_EN |
|
||
|
|
MDP4_DMA_CONFIG_DITHER_EN;
|
||
|
|
|
||
|
|
if (!of_property_read_bool(dev->dev->of_node, "qcom,lcdc-align-lsb"))
|
||
|
|
config |= MDP4_DMA_CONFIG_PACK_ALIGN_MSB;
|
||
|
|
|
||
|
|
mdp4_crtc_set_config(encoder->crtc, config);
|
||
|
|
mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 0);
|
||
|
|
|
||
|
|
for (i = 0; i < ARRAY_SIZE(mdp4_lcdc_encoder->regs); i++) {
|
||
|
|
ret = regulator_enable(mdp4_lcdc_encoder->regs[i]);
|
||
|
|
if (ret)
|
||
|
|
DRM_DEV_ERROR(dev->dev, "failed to enable regulator: %d\n", ret);
|
||
|
|
}
|
||
|
|
|
||
|
|
DBG("setting lcdc_clk=%lu", pc);
|
||
|
|
ret = clk_set_rate(mdp4_lcdc_encoder->lcdc_clk, pc);
|
||
|
|
if (ret)
|
||
|
|
DRM_DEV_ERROR(dev->dev, "failed to configure lcdc_clk: %d\n", ret);
|
||
|
|
ret = clk_prepare_enable(mdp4_lcdc_encoder->lcdc_clk);
|
||
|
|
if (ret)
|
||
|
|
DRM_DEV_ERROR(dev->dev, "failed to enable lcdc_clk: %d\n", ret);
|
||
|
|
|
||
|
|
panel = of_drm_find_panel(mdp4_lcdc_encoder->panel_node);
|
||
|
|
if (!IS_ERR(panel)) {
|
||
|
|
drm_panel_prepare(panel);
|
||
|
|
drm_panel_enable(panel);
|
||
|
|
}
|
||
|
|
|
||
|
|
setup_phy(encoder);
|
||
|
|
|
||
|
|
mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 1);
|
||
|
|
|
||
|
|
mdp4_lcdc_encoder->enabled = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct drm_encoder_helper_funcs mdp4_lcdc_encoder_helper_funcs = {
|
||
|
|
.mode_set = mdp4_lcdc_encoder_mode_set,
|
||
|
|
.disable = mdp4_lcdc_encoder_disable,
|
||
|
|
.enable = mdp4_lcdc_encoder_enable,
|
||
|
|
};
|
||
|
|
|
||
|
|
long mdp4_lcdc_round_pixclk(struct drm_encoder *encoder, unsigned long rate)
|
||
|
|
{
|
||
|
|
struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
|
||
|
|
to_mdp4_lcdc_encoder(encoder);
|
||
|
|
return clk_round_rate(mdp4_lcdc_encoder->lcdc_clk, rate);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* initialize encoder */
|
||
|
|
struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev,
|
||
|
|
struct device_node *panel_node)
|
||
|
|
{
|
||
|
|
struct drm_encoder *encoder = NULL;
|
||
|
|
struct mdp4_lcdc_encoder *mdp4_lcdc_encoder;
|
||
|
|
struct regulator *reg;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
mdp4_lcdc_encoder = kzalloc(sizeof(*mdp4_lcdc_encoder), GFP_KERNEL);
|
||
|
|
if (!mdp4_lcdc_encoder) {
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
mdp4_lcdc_encoder->panel_node = panel_node;
|
||
|
|
|
||
|
|
encoder = &mdp4_lcdc_encoder->base;
|
||
|
|
|
||
|
|
drm_encoder_init(dev, encoder, &mdp4_lcdc_encoder_funcs,
|
||
|
|
DRM_MODE_ENCODER_LVDS, NULL);
|
||
|
|
drm_encoder_helper_add(encoder, &mdp4_lcdc_encoder_helper_funcs);
|
||
|
|
|
||
|
|
/* TODO: do we need different pll in other cases? */
|
||
|
|
mdp4_lcdc_encoder->lcdc_clk = mpd4_lvds_pll_init(dev);
|
||
|
|
if (IS_ERR(mdp4_lcdc_encoder->lcdc_clk)) {
|
||
|
|
DRM_DEV_ERROR(dev->dev, "failed to get lvds_clk\n");
|
||
|
|
ret = PTR_ERR(mdp4_lcdc_encoder->lcdc_clk);
|
||
|
|
goto fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* TODO: different regulators in other cases? */
|
||
|
|
reg = devm_regulator_get(dev->dev, "lvds-vccs-3p3v");
|
||
|
|
if (IS_ERR(reg)) {
|
||
|
|
ret = PTR_ERR(reg);
|
||
|
|
DRM_DEV_ERROR(dev->dev, "failed to get lvds-vccs-3p3v: %d\n", ret);
|
||
|
|
goto fail;
|
||
|
|
}
|
||
|
|
mdp4_lcdc_encoder->regs[0] = reg;
|
||
|
|
|
||
|
|
reg = devm_regulator_get(dev->dev, "lvds-pll-vdda");
|
||
|
|
if (IS_ERR(reg)) {
|
||
|
|
ret = PTR_ERR(reg);
|
||
|
|
DRM_DEV_ERROR(dev->dev, "failed to get lvds-pll-vdda: %d\n", ret);
|
||
|
|
goto fail;
|
||
|
|
}
|
||
|
|
mdp4_lcdc_encoder->regs[1] = reg;
|
||
|
|
|
||
|
|
reg = devm_regulator_get(dev->dev, "lvds-vdda");
|
||
|
|
if (IS_ERR(reg)) {
|
||
|
|
ret = PTR_ERR(reg);
|
||
|
|
DRM_DEV_ERROR(dev->dev, "failed to get lvds-vdda: %d\n", ret);
|
||
|
|
goto fail;
|
||
|
|
}
|
||
|
|
mdp4_lcdc_encoder->regs[2] = reg;
|
||
|
|
|
||
|
|
return encoder;
|
||
|
|
|
||
|
|
fail:
|
||
|
|
if (encoder)
|
||
|
|
mdp4_lcdc_encoder_destroy(encoder);
|
||
|
|
|
||
|
|
return ERR_PTR(ret);
|
||
|
|
}
|