198 lines
6.2 KiB
C
198 lines
6.2 KiB
C
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/*
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* Copyright 2021 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <subdev/acr.h>
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#include <subdev/vfn.h>
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#include <nvfw/flcn.h>
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#include <nvfw/sec2.h>
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static int
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ga102_sec2_initmsg(struct nvkm_sec2 *sec2)
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{
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struct nv_sec2_init_msg_v1 msg;
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int ret, i;
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ret = nvkm_falcon_msgq_recv_initmsg(sec2->msgq, &msg, sizeof(msg));
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if (ret)
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return ret;
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if (msg.hdr.unit_id != NV_SEC2_UNIT_INIT ||
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msg.msg_type != NV_SEC2_INIT_MSG_INIT)
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(msg.queue_info); i++) {
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if (msg.queue_info[i].id == NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ) {
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nvkm_falcon_msgq_init(sec2->msgq, msg.queue_info[i].index,
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msg.queue_info[i].offset,
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msg.queue_info[i].size);
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} else {
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nvkm_falcon_cmdq_init(sec2->cmdq, msg.queue_info[i].index,
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msg.queue_info[i].offset,
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msg.queue_info[i].size);
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}
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}
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return 0;
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}
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static struct nvkm_intr *
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ga102_sec2_intr_vector(struct nvkm_sec2 *sec2, enum nvkm_intr_type *pvector)
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{
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struct nvkm_device *device = sec2->engine.subdev.device;
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struct nvkm_falcon *falcon = &sec2->falcon;
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int ret;
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ret = ga102_flcn_select(falcon);
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if (ret)
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return ERR_PTR(ret);
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*pvector = nvkm_rd32(device, 0x8403e0) & 0x000000ff;
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return &device->vfn->intr;
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}
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static int
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ga102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nvfw_falcon_msg *hdr)
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{
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struct nv_sec2_acr_bootstrap_falcon_msg_v1 *msg =
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container_of(hdr, typeof(*msg), msg.hdr);
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struct nvkm_subdev *subdev = priv;
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const char *name = nvkm_acr_lsf_id(msg->falcon_id);
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if (msg->error_code) {
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nvkm_error(subdev, "ACR_BOOTSTRAP_FALCON failed for falcon %d [%s]: %08x %08x\n",
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msg->falcon_id, name, msg->error_code, msg->unkn08);
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return -EINVAL;
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}
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nvkm_debug(subdev, "%s booted\n", name);
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return 0;
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}
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static int
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ga102_sec2_acr_bootstrap_falcon(struct nvkm_falcon *falcon, enum nvkm_acr_lsf_id id)
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{
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struct nvkm_sec2 *sec2 = container_of(falcon, typeof(*sec2), falcon);
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struct nv_sec2_acr_bootstrap_falcon_cmd_v1 cmd = {
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.cmd.hdr.unit_id = sec2->func->unit_acr,
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.cmd.hdr.size = sizeof(cmd),
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.cmd.cmd_type = NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON,
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.flags = NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES,
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.falcon_id = id,
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};
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return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr,
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ga102_sec2_acr_bootstrap_falcon_callback,
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&sec2->engine.subdev,
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msecs_to_jiffies(1000));
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}
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static const struct nvkm_acr_lsf_func
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ga102_sec2_acr_0 = {
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.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
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.bld_write = gp102_sec2_acr_bld_write_1,
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.bld_patch = gp102_sec2_acr_bld_patch_1,
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.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
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BIT_ULL(NVKM_ACR_LSF_GPCCS) |
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BIT_ULL(NVKM_ACR_LSF_SEC2),
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.bootstrap_falcon = ga102_sec2_acr_bootstrap_falcon,
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};
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static const struct nvkm_falcon_func
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ga102_sec2_flcn = {
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.disable = gm200_flcn_disable,
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.enable = gm200_flcn_enable,
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.select = ga102_flcn_select,
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.addr2 = 0x1000,
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.reset_pmc = true,
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.reset_eng = gp102_flcn_reset_eng,
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.reset_prep = ga102_flcn_reset_prep,
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.reset_wait_mem_scrubbing = ga102_flcn_reset_wait_mem_scrubbing,
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.imem_dma = &ga102_flcn_dma,
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.dmem_pio = &gm200_flcn_dmem_pio,
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.dmem_dma = &ga102_flcn_dma,
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.emem_addr = 0x01000000,
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.emem_pio = &gp102_flcn_emem_pio,
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.start = nvkm_falcon_v1_start,
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.cmdq = { 0xc00, 0xc04, 8 },
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.msgq = { 0xc80, 0xc84, 8 },
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};
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static const struct nvkm_sec2_func
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ga102_sec2 = {
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.flcn = &ga102_sec2_flcn,
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.intr_vector = ga102_sec2_intr_vector,
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.intr = gp102_sec2_intr,
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.initmsg = ga102_sec2_initmsg,
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.unit_acr = NV_SEC2_UNIT_V2_ACR,
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.unit_unload = NV_SEC2_UNIT_V2_UNLOAD,
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};
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MODULE_FIRMWARE("nvidia/ga102/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/ga102/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/ga102/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/ga102/sec2/hs_bl_sig.bin");
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MODULE_FIRMWARE("nvidia/ga103/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/ga103/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/ga103/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/ga103/sec2/hs_bl_sig.bin");
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MODULE_FIRMWARE("nvidia/ga104/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/ga104/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/ga104/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/ga104/sec2/hs_bl_sig.bin");
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MODULE_FIRMWARE("nvidia/ga106/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/ga106/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/ga106/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/ga106/sec2/hs_bl_sig.bin");
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MODULE_FIRMWARE("nvidia/ga107/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/ga107/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/ga107/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/ga107/sec2/hs_bl_sig.bin");
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static int
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ga102_sec2_load(struct nvkm_sec2 *sec2, int ver,
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const struct nvkm_sec2_fwif *fwif)
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{
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return nvkm_acr_lsfw_load_sig_image_desc_v2(&sec2->engine.subdev, &sec2->falcon,
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NVKM_ACR_LSF_SEC2, "sec2/", ver, fwif->acr);
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}
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static const struct nvkm_sec2_fwif
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ga102_sec2_fwif[] = {
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{ 0, ga102_sec2_load, &ga102_sec2, &ga102_sec2_acr_0 },
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{ -1, gp102_sec2_nofw, &ga102_sec2 }
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};
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int
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ga102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_sec2 **psec2)
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{
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/* TOP info wasn't updated on Turing to reflect the PRI
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* address change for some reason. We override it here.
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*/
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return nvkm_sec2_new_(ga102_sec2_fwif, device, type, inst, 0x840000, psec2);
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}
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