271 lines
7.6 KiB
C
271 lines
7.6 KiB
C
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <core/memory.h>
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#include <subdev/acr.h>
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#include <nvfw/flcn.h>
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#include <nvfw/pmu.h>
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static int
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gm20b_pmu_acr_bootstrap_falcon_cb(void *priv, struct nvfw_falcon_msg *hdr)
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{
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struct nv_pmu_acr_bootstrap_falcon_msg *msg =
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container_of(hdr, typeof(*msg), msg.hdr);
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return msg->falcon_id;
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}
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int
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gm20b_pmu_acr_bootstrap_falcon(struct nvkm_falcon *falcon,
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enum nvkm_acr_lsf_id id)
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{
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struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon);
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struct nv_pmu_acr_bootstrap_falcon_cmd cmd = {
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.cmd.hdr.unit_id = NV_PMU_UNIT_ACR,
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.cmd.hdr.size = sizeof(cmd),
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.cmd.cmd_type = NV_PMU_ACR_CMD_BOOTSTRAP_FALCON,
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.flags = NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES,
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.falcon_id = id,
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};
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int ret;
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ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr,
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gm20b_pmu_acr_bootstrap_falcon_cb,
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&pmu->subdev, msecs_to_jiffies(1000));
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if (ret >= 0) {
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if (ret != cmd.falcon_id)
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ret = -EIO;
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else
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ret = 0;
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}
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return ret;
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}
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void
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gm20b_pmu_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
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{
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struct loader_config hdr;
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u64 addr;
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nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
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addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8);
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hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8);
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hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8);
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addr = ((u64)hdr.data_dma_base1 << 40 | hdr.data_dma_base << 8);
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hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8);
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hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8);
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addr = ((u64)hdr.overlay_dma_base1 << 40 | hdr.overlay_dma_base << 8);
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hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8);
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hdr.overlay_dma_base1 = upper_32_bits((addr + adjust) << 8);
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nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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loader_config_dump(&acr->subdev, &hdr);
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}
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void
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gm20b_pmu_acr_bld_write(struct nvkm_acr *acr, u32 bld,
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struct nvkm_acr_lsfw *lsfw)
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{
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const u64 base = lsfw->offset.img + lsfw->app_start_offset;
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const u64 code = (base + lsfw->app_resident_code_offset) >> 8;
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const u64 data = (base + lsfw->app_resident_data_offset) >> 8;
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const struct loader_config hdr = {
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.dma_idx = FALCON_DMAIDX_UCODE,
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.code_dma_base = lower_32_bits(code),
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.code_size_total = lsfw->app_size,
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.code_size_to_load = lsfw->app_resident_code_size,
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.code_entry_point = lsfw->app_imem_entry,
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.data_dma_base = lower_32_bits(data),
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.data_size = lsfw->app_resident_data_size,
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.overlay_dma_base = lower_32_bits(code),
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.argc = 1,
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.argv = lsfw->falcon->data.limit - sizeof(struct nv_pmu_args),
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.code_dma_base1 = upper_32_bits(code),
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.data_dma_base1 = upper_32_bits(data),
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.overlay_dma_base1 = upper_32_bits(code),
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};
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nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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}
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static const struct nvkm_acr_lsf_func
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gm20b_pmu_acr = {
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.flags = NVKM_ACR_LSF_DMACTL_REQ_CTX,
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.bld_size = sizeof(struct loader_config),
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.bld_write = gm20b_pmu_acr_bld_write,
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.bld_patch = gm20b_pmu_acr_bld_patch,
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.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_PMU) |
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BIT_ULL(NVKM_ACR_LSF_FECS) |
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BIT_ULL(NVKM_ACR_LSF_GPCCS),
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.bootstrap_falcon = gm20b_pmu_acr_bootstrap_falcon,
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};
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static int
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gm20b_pmu_acr_init_wpr_callback(void *priv, struct nvfw_falcon_msg *hdr)
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{
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struct nv_pmu_acr_init_wpr_region_msg *msg =
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container_of(hdr, typeof(*msg), msg.hdr);
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struct nvkm_pmu *pmu = priv;
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struct nvkm_subdev *subdev = &pmu->subdev;
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if (msg->error_code) {
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nvkm_error(subdev, "ACR WPR init failure: %d\n",
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msg->error_code);
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return -EINVAL;
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}
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nvkm_debug(subdev, "ACR WPR init complete\n");
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complete_all(&pmu->wpr_ready);
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return 0;
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}
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static int
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gm20b_pmu_acr_init_wpr(struct nvkm_pmu *pmu)
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{
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struct nv_pmu_acr_init_wpr_region_cmd cmd = {
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.cmd.hdr.unit_id = NV_PMU_UNIT_ACR,
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.cmd.hdr.size = sizeof(cmd),
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.cmd.cmd_type = NV_PMU_ACR_CMD_INIT_WPR_REGION,
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.region_id = 1,
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.wpr_offset = 0,
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};
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return nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr,
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gm20b_pmu_acr_init_wpr_callback, pmu, 0);
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}
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static int
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gm20b_pmu_initmsg(struct nvkm_pmu *pmu)
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{
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struct nv_pmu_init_msg msg;
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int ret;
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ret = nvkm_falcon_msgq_recv_initmsg(pmu->msgq, &msg, sizeof(msg));
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if (ret)
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return ret;
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if (msg.hdr.unit_id != NV_PMU_UNIT_INIT ||
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msg.msg_type != NV_PMU_INIT_MSG_INIT)
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return -EINVAL;
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nvkm_falcon_cmdq_init(pmu->hpq, msg.queue_info[0].index,
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msg.queue_info[0].offset,
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msg.queue_info[0].size);
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nvkm_falcon_cmdq_init(pmu->lpq, msg.queue_info[1].index,
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msg.queue_info[1].offset,
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msg.queue_info[1].size);
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nvkm_falcon_msgq_init(pmu->msgq, msg.queue_info[4].index,
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msg.queue_info[4].offset,
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msg.queue_info[4].size);
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return gm20b_pmu_acr_init_wpr(pmu);
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}
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static void
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gm20b_pmu_recv(struct nvkm_pmu *pmu)
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{
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if (!pmu->initmsg_received) {
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int ret = pmu->func->initmsg(pmu);
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if (ret) {
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nvkm_error(&pmu->subdev, "error parsing init message: %d\n", ret);
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return;
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}
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pmu->initmsg_received = true;
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}
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nvkm_falcon_msgq_recv(pmu->msgq);
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}
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static void
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gm20b_pmu_fini(struct nvkm_pmu *pmu)
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{
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/*TODO: shutdown RTOS. */
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flush_work(&pmu->recv.work);
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nvkm_falcon_cmdq_fini(pmu->lpq);
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nvkm_falcon_cmdq_fini(pmu->hpq);
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reinit_completion(&pmu->wpr_ready);
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nvkm_falcon_put(&pmu->falcon, &pmu->subdev);
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}
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static int
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gm20b_pmu_init(struct nvkm_pmu *pmu)
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{
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struct nvkm_falcon *falcon = &pmu->falcon;
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struct nv_pmu_args args = { .secure_mode = true };
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u32 addr_args = falcon->data.limit - sizeof(args);
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int ret;
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ret = nvkm_falcon_get(&pmu->falcon, &pmu->subdev);
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if (ret)
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return ret;
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pmu->initmsg_received = false;
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nvkm_falcon_pio_wr(falcon, (u8 *)&args, 0, 0, DMEM, addr_args, sizeof(args), 0, false);
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nvkm_falcon_start(falcon);
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return 0;
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}
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const struct nvkm_pmu_func
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gm20b_pmu = {
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.flcn = &gm200_pmu_flcn,
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.init = gm20b_pmu_init,
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.fini = gm20b_pmu_fini,
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.intr = gt215_pmu_intr,
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.recv = gm20b_pmu_recv,
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.initmsg = gm20b_pmu_initmsg,
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.reset = gf100_pmu_reset,
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};
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
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MODULE_FIRMWARE("nvidia/gm20b/pmu/desc.bin");
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MODULE_FIRMWARE("nvidia/gm20b/pmu/image.bin");
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MODULE_FIRMWARE("nvidia/gm20b/pmu/sig.bin");
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#endif
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int
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gm20b_pmu_load(struct nvkm_pmu *pmu, int ver, const struct nvkm_pmu_fwif *fwif)
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{
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return nvkm_acr_lsfw_load_sig_image_desc(&pmu->subdev, &pmu->falcon,
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NVKM_ACR_LSF_PMU, "pmu/",
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ver, fwif->acr);
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}
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static const struct nvkm_pmu_fwif
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gm20b_pmu_fwif[] = {
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{ 0, gm20b_pmu_load, &gm20b_pmu, &gm20b_pmu_acr },
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{ -1, gm200_pmu_nofw, &gm20b_pmu },
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{}
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};
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int
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gm20b_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_pmu **ppmu)
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{
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return nvkm_pmu_new_(gm20b_pmu_fwif, device, type, inst, ppmu);
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}
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