298 lines
7.7 KiB
C
298 lines
7.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* HDMI wrapper
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#define DSS_SUBSYS_NAME "HDMIWP"
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/seq_file.h>
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#include "omapdss.h"
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#include "dss.h"
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#include "hdmi.h"
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void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)
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{
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#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))
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DUMPREG(HDMI_WP_REVISION);
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DUMPREG(HDMI_WP_SYSCONFIG);
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DUMPREG(HDMI_WP_IRQSTATUS_RAW);
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DUMPREG(HDMI_WP_IRQSTATUS);
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DUMPREG(HDMI_WP_IRQENABLE_SET);
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DUMPREG(HDMI_WP_IRQENABLE_CLR);
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DUMPREG(HDMI_WP_IRQWAKEEN);
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DUMPREG(HDMI_WP_PWR_CTRL);
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DUMPREG(HDMI_WP_DEBOUNCE);
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DUMPREG(HDMI_WP_VIDEO_CFG);
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DUMPREG(HDMI_WP_VIDEO_SIZE);
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DUMPREG(HDMI_WP_VIDEO_TIMING_H);
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DUMPREG(HDMI_WP_VIDEO_TIMING_V);
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DUMPREG(HDMI_WP_CLK);
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DUMPREG(HDMI_WP_AUDIO_CFG);
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DUMPREG(HDMI_WP_AUDIO_CFG2);
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DUMPREG(HDMI_WP_AUDIO_CTRL);
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DUMPREG(HDMI_WP_AUDIO_DATA);
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}
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u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)
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{
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return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
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}
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void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)
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{
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hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);
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/* flush posted write */
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hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
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}
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void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)
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{
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hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);
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}
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void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)
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{
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hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);
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}
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/* PHY_PWR_CMD */
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int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)
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{
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/* Return if already the state */
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if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)
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return 0;
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/* Command for power control of HDMI PHY */
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REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);
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/* Status of the power control of HDMI PHY */
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if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)
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!= val) {
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DSSERR("Failed to set PHY power mode to %d\n", val);
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return -ETIMEDOUT;
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}
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return 0;
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}
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/* PLL_PWR_CMD */
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int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)
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{
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/* Command for power control of HDMI PLL */
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REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);
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/* wait till PHY_PWR_STATUS is set */
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if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)
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!= val) {
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DSSERR("Failed to set PLL_PWR_STATUS\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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int hdmi_wp_video_start(struct hdmi_wp_data *wp)
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{
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REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);
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return 0;
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}
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void hdmi_wp_video_stop(struct hdmi_wp_data *wp)
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{
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int i;
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hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE);
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REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);
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for (i = 0; i < 50; ++i) {
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u32 v;
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msleep(20);
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v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);
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if (v & HDMI_IRQ_VIDEO_FRAME_DONE)
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return;
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}
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DSSERR("no HDMI FRAMEDONE when disabling output\n");
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}
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void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
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const struct hdmi_video_format *video_fmt)
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{
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u32 l = 0;
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REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,
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10, 8);
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l |= FLD_VAL(video_fmt->y_res, 31, 16);
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l |= FLD_VAL(video_fmt->x_res, 15, 0);
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hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);
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}
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void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
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const struct videomode *vm)
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{
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u32 r;
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bool vsync_inv, hsync_inv;
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DSSDBG("Enter hdmi_wp_video_config_interface\n");
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vsync_inv = !!(vm->flags & DISPLAY_FLAGS_VSYNC_LOW);
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hsync_inv = !!(vm->flags & DISPLAY_FLAGS_HSYNC_LOW);
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r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
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r = FLD_MOD(r, 1, 7, 7); /* VSYNC_POL to dispc active high */
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r = FLD_MOD(r, 1, 6, 6); /* HSYNC_POL to dispc active high */
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r = FLD_MOD(r, vsync_inv, 5, 5); /* CORE_VSYNC_INV */
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r = FLD_MOD(r, hsync_inv, 4, 4); /* CORE_HSYNC_INV */
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r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 3, 3);
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r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
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hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
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}
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void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
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const struct videomode *vm)
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{
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u32 timing_h = 0;
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u32 timing_v = 0;
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unsigned int hsync_len_offset = 1;
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DSSDBG("Enter hdmi_wp_video_config_timing\n");
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/*
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* On OMAP4 and OMAP5 ES1 the HSW field is programmed as is. On OMAP5
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* ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsync_len-1.
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* However, we don't support OMAP5 ES1 at all, so we can just check for
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* OMAP4 here.
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*/
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if (wp->version == 4)
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hsync_len_offset = 0;
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timing_h |= FLD_VAL(vm->hback_porch, 31, 20);
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timing_h |= FLD_VAL(vm->hfront_porch, 19, 8);
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timing_h |= FLD_VAL(vm->hsync_len - hsync_len_offset, 7, 0);
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hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
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timing_v |= FLD_VAL(vm->vback_porch, 31, 20);
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timing_v |= FLD_VAL(vm->vfront_porch, 19, 8);
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timing_v |= FLD_VAL(vm->vsync_len, 7, 0);
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hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
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}
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void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
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struct videomode *vm, const struct hdmi_config *param)
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{
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DSSDBG("Enter hdmi_wp_video_init_format\n");
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video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
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video_fmt->y_res = param->vm.vactive;
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video_fmt->x_res = param->vm.hactive;
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vm->hback_porch = param->vm.hback_porch;
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vm->hfront_porch = param->vm.hfront_porch;
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vm->hsync_len = param->vm.hsync_len;
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vm->vback_porch = param->vm.vback_porch;
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vm->vfront_porch = param->vm.vfront_porch;
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vm->vsync_len = param->vm.vsync_len;
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vm->flags = param->vm.flags;
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if (param->vm.flags & DISPLAY_FLAGS_INTERLACED) {
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video_fmt->y_res /= 2;
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vm->vback_porch /= 2;
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vm->vfront_porch /= 2;
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vm->vsync_len /= 2;
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}
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if (param->vm.flags & DISPLAY_FLAGS_DOUBLECLK) {
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video_fmt->x_res *= 2;
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vm->hfront_porch *= 2;
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vm->hsync_len *= 2;
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vm->hback_porch *= 2;
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}
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}
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void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
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struct hdmi_audio_format *aud_fmt)
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{
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u32 r;
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DSSDBG("Enter hdmi_wp_audio_config_format\n");
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r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);
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if (wp->version == 4) {
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r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
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r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
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}
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r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
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r = FLD_MOD(r, aud_fmt->type, 4, 4);
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r = FLD_MOD(r, aud_fmt->justification, 3, 3);
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r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
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r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
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r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
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hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);
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}
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void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
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struct hdmi_audio_dma *aud_dma)
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{
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u32 r;
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DSSDBG("Enter hdmi_wp_audio_config_dma\n");
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r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);
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r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
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r = FLD_MOD(r, aud_dma->block_size, 7, 0);
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hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);
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r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);
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r = FLD_MOD(r, aud_dma->mode, 9, 9);
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r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
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hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);
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}
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int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)
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{
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REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);
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return 0;
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}
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int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)
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{
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REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);
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return 0;
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}
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int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp,
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unsigned int version)
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{
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struct resource *res;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp");
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wp->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(wp->base))
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return PTR_ERR(wp->base);
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wp->phys_base = res->start;
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wp->version = version;
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return 0;
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}
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phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)
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{
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return wp->phys_base + HDMI_WP_AUDIO_DATA;
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}
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