393 lines
10 KiB
C
393 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Toppoly TD028TTEC1 Panel Driver
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*
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* Copyright (C) 2019 Texas Instruments Incorporated
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*
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* Based on the omapdrm-specific panel-tpo-td028ttec1 driver
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*
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* Copyright (C) 2008 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
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*
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* Neo 1973 code (jbt6k74.c):
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* Copyright (C) 2006-2007 OpenMoko, Inc.
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* Author: Harald Welte <laforge@openmoko.org>
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*
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* Ported and adapted from Neo 1973 U-Boot by:
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* H. Nikolaus Schaller <hns@goldelico.com>
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*/
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/spi/spi.h>
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#include <drm/drm_connector.h>
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#include <drm/drm_modes.h>
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#include <drm/drm_panel.h>
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#define JBT_COMMAND 0x000
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#define JBT_DATA 0x100
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#define JBT_REG_SLEEP_IN 0x10
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#define JBT_REG_SLEEP_OUT 0x11
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#define JBT_REG_DISPLAY_OFF 0x28
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#define JBT_REG_DISPLAY_ON 0x29
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#define JBT_REG_RGB_FORMAT 0x3a
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#define JBT_REG_QUAD_RATE 0x3b
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#define JBT_REG_POWER_ON_OFF 0xb0
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#define JBT_REG_BOOSTER_OP 0xb1
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#define JBT_REG_BOOSTER_MODE 0xb2
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#define JBT_REG_BOOSTER_FREQ 0xb3
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#define JBT_REG_OPAMP_SYSCLK 0xb4
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#define JBT_REG_VSC_VOLTAGE 0xb5
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#define JBT_REG_VCOM_VOLTAGE 0xb6
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#define JBT_REG_EXT_DISPL 0xb7
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#define JBT_REG_OUTPUT_CONTROL 0xb8
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#define JBT_REG_DCCLK_DCEV 0xb9
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#define JBT_REG_DISPLAY_MODE1 0xba
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#define JBT_REG_DISPLAY_MODE2 0xbb
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#define JBT_REG_DISPLAY_MODE 0xbc
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#define JBT_REG_ASW_SLEW 0xbd
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#define JBT_REG_DUMMY_DISPLAY 0xbe
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#define JBT_REG_DRIVE_SYSTEM 0xbf
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#define JBT_REG_SLEEP_OUT_FR_A 0xc0
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#define JBT_REG_SLEEP_OUT_FR_B 0xc1
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#define JBT_REG_SLEEP_OUT_FR_C 0xc2
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#define JBT_REG_SLEEP_IN_LCCNT_D 0xc3
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#define JBT_REG_SLEEP_IN_LCCNT_E 0xc4
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#define JBT_REG_SLEEP_IN_LCCNT_F 0xc5
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#define JBT_REG_SLEEP_IN_LCCNT_G 0xc6
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#define JBT_REG_GAMMA1_FINE_1 0xc7
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#define JBT_REG_GAMMA1_FINE_2 0xc8
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#define JBT_REG_GAMMA1_INCLINATION 0xc9
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#define JBT_REG_GAMMA1_BLUE_OFFSET 0xca
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#define JBT_REG_BLANK_CONTROL 0xcf
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#define JBT_REG_BLANK_TH_TV 0xd0
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#define JBT_REG_CKV_ON_OFF 0xd1
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#define JBT_REG_CKV_1_2 0xd2
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#define JBT_REG_OEV_TIMING 0xd3
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#define JBT_REG_ASW_TIMING_1 0xd4
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#define JBT_REG_ASW_TIMING_2 0xd5
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#define JBT_REG_HCLOCK_VGA 0xec
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#define JBT_REG_HCLOCK_QVGA 0xed
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struct td028ttec1_panel {
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struct drm_panel panel;
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struct spi_device *spi;
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};
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#define to_td028ttec1_device(p) container_of(p, struct td028ttec1_panel, panel)
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/*
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* noinline_for_stack so we don't get multiple copies of tx_buf
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* on the stack in case of gcc-plugin-structleak
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*/
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static int noinline_for_stack
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jbt_ret_write_0(struct td028ttec1_panel *lcd, u8 reg, int *err)
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{
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struct spi_device *spi = lcd->spi;
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u16 tx_buf = JBT_COMMAND | reg;
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int ret;
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if (err && *err)
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return *err;
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ret = spi_write(spi, (u8 *)&tx_buf, sizeof(tx_buf));
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if (ret < 0) {
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dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
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if (err)
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*err = ret;
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}
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return ret;
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}
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static int noinline_for_stack
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jbt_reg_write_1(struct td028ttec1_panel *lcd,
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u8 reg, u8 data, int *err)
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{
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struct spi_device *spi = lcd->spi;
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u16 tx_buf[2];
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int ret;
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if (err && *err)
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return *err;
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tx_buf[0] = JBT_COMMAND | reg;
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tx_buf[1] = JBT_DATA | data;
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ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
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if (ret < 0) {
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dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
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if (err)
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*err = ret;
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}
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return ret;
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}
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static int noinline_for_stack
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jbt_reg_write_2(struct td028ttec1_panel *lcd,
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u8 reg, u16 data, int *err)
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{
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struct spi_device *spi = lcd->spi;
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u16 tx_buf[3];
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int ret;
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if (err && *err)
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return *err;
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tx_buf[0] = JBT_COMMAND | reg;
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tx_buf[1] = JBT_DATA | (data >> 8);
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tx_buf[2] = JBT_DATA | (data & 0xff);
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ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
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if (ret < 0) {
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dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
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if (err)
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*err = ret;
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}
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return ret;
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}
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static int td028ttec1_prepare(struct drm_panel *panel)
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{
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struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
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unsigned int i;
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int ret = 0;
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/* Three times command zero */
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for (i = 0; i < 3; ++i) {
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jbt_ret_write_0(lcd, 0x00, &ret);
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usleep_range(1000, 2000);
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}
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/* deep standby out */
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jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x17, &ret);
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/* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
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jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE, 0x80, &ret);
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/* Quad mode off */
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jbt_reg_write_1(lcd, JBT_REG_QUAD_RATE, 0x00, &ret);
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/* AVDD on, XVDD on */
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jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x16, &ret);
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/* Output control */
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jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0xfff9, &ret);
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/* Sleep mode off */
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jbt_ret_write_0(lcd, JBT_REG_SLEEP_OUT, &ret);
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/* at this point we have like 50% grey */
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/* initialize register set */
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jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE1, 0x01, &ret);
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jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE2, 0x00, &ret);
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jbt_reg_write_1(lcd, JBT_REG_RGB_FORMAT, 0x60, &ret);
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jbt_reg_write_1(lcd, JBT_REG_DRIVE_SYSTEM, 0x10, &ret);
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jbt_reg_write_1(lcd, JBT_REG_BOOSTER_OP, 0x56, &ret);
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jbt_reg_write_1(lcd, JBT_REG_BOOSTER_MODE, 0x33, &ret);
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jbt_reg_write_1(lcd, JBT_REG_BOOSTER_FREQ, 0x11, &ret);
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jbt_reg_write_1(lcd, JBT_REG_BOOSTER_FREQ, 0x11, &ret);
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jbt_reg_write_1(lcd, JBT_REG_OPAMP_SYSCLK, 0x02, &ret);
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jbt_reg_write_1(lcd, JBT_REG_VSC_VOLTAGE, 0x2b, &ret);
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jbt_reg_write_1(lcd, JBT_REG_VCOM_VOLTAGE, 0x40, &ret);
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jbt_reg_write_1(lcd, JBT_REG_EXT_DISPL, 0x03, &ret);
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jbt_reg_write_1(lcd, JBT_REG_DCCLK_DCEV, 0x04, &ret);
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/*
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* default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
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* to avoid red / blue flicker
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*/
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jbt_reg_write_1(lcd, JBT_REG_ASW_SLEW, 0x04, &ret);
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jbt_reg_write_1(lcd, JBT_REG_DUMMY_DISPLAY, 0x00, &ret);
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jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_A, 0x11, &ret);
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jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_B, 0x11, &ret);
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jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_C, 0x11, &ret);
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jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040, &ret);
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jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0, &ret);
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jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020, &ret);
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jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0, &ret);
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jbt_reg_write_2(lcd, JBT_REG_GAMMA1_FINE_1, 0x5533, &ret);
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jbt_reg_write_1(lcd, JBT_REG_GAMMA1_FINE_2, 0x00, &ret);
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jbt_reg_write_1(lcd, JBT_REG_GAMMA1_INCLINATION, 0x00, &ret);
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jbt_reg_write_1(lcd, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00, &ret);
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jbt_reg_write_2(lcd, JBT_REG_HCLOCK_VGA, 0x1f0, &ret);
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jbt_reg_write_1(lcd, JBT_REG_BLANK_CONTROL, 0x02, &ret);
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jbt_reg_write_2(lcd, JBT_REG_BLANK_TH_TV, 0x0804, &ret);
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jbt_reg_write_1(lcd, JBT_REG_CKV_ON_OFF, 0x01, &ret);
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jbt_reg_write_2(lcd, JBT_REG_CKV_1_2, 0x0000, &ret);
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jbt_reg_write_2(lcd, JBT_REG_OEV_TIMING, 0x0d0e, &ret);
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jbt_reg_write_2(lcd, JBT_REG_ASW_TIMING_1, 0x11a4, &ret);
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jbt_reg_write_1(lcd, JBT_REG_ASW_TIMING_2, 0x0e, &ret);
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return ret;
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}
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static int td028ttec1_enable(struct drm_panel *panel)
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{
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struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
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return jbt_ret_write_0(lcd, JBT_REG_DISPLAY_ON, NULL);
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}
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static int td028ttec1_disable(struct drm_panel *panel)
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{
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struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
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jbt_ret_write_0(lcd, JBT_REG_DISPLAY_OFF, NULL);
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return 0;
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}
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static int td028ttec1_unprepare(struct drm_panel *panel)
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{
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struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
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jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0x8002, NULL);
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jbt_ret_write_0(lcd, JBT_REG_SLEEP_IN, NULL);
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jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x00, NULL);
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return 0;
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}
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static const struct drm_display_mode td028ttec1_mode = {
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.clock = 22153,
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.hdisplay = 480,
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.hsync_start = 480 + 24,
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.hsync_end = 480 + 24 + 8,
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.htotal = 480 + 24 + 8 + 8,
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.vdisplay = 640,
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.vsync_start = 640 + 4,
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.vsync_end = 640 + 4 + 2,
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.vtotal = 640 + 4 + 2 + 2,
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.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
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.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
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.width_mm = 43,
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.height_mm = 58,
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};
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static int td028ttec1_get_modes(struct drm_panel *panel,
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struct drm_connector *connector)
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{
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struct drm_display_mode *mode;
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mode = drm_mode_duplicate(connector->dev, &td028ttec1_mode);
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if (!mode)
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return -ENOMEM;
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drm_mode_set_name(mode);
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drm_mode_probed_add(connector, mode);
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connector->display_info.width_mm = td028ttec1_mode.width_mm;
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connector->display_info.height_mm = td028ttec1_mode.height_mm;
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/*
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* FIXME: According to the datasheet sync signals are sampled on the
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* rising edge of the clock, but the code running on the OpenMoko Neo
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* FreeRunner and Neo 1973 indicates sampling on the falling edge. This
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* should be tested on a real device.
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*/
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connector->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH
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| DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
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| DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE;
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return 1;
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}
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static const struct drm_panel_funcs td028ttec1_funcs = {
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.prepare = td028ttec1_prepare,
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.enable = td028ttec1_enable,
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.disable = td028ttec1_disable,
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.unprepare = td028ttec1_unprepare,
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.get_modes = td028ttec1_get_modes,
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};
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static int td028ttec1_probe(struct spi_device *spi)
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{
|
||
|
|
struct td028ttec1_panel *lcd;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
lcd = devm_kzalloc(&spi->dev, sizeof(*lcd), GFP_KERNEL);
|
||
|
|
if (!lcd)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
spi_set_drvdata(spi, lcd);
|
||
|
|
lcd->spi = spi;
|
||
|
|
|
||
|
|
spi->mode = SPI_MODE_3;
|
||
|
|
spi->bits_per_word = 9;
|
||
|
|
|
||
|
|
ret = spi_setup(spi);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(&spi->dev, "failed to setup SPI: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
drm_panel_init(&lcd->panel, &lcd->spi->dev, &td028ttec1_funcs,
|
||
|
|
DRM_MODE_CONNECTOR_DPI);
|
||
|
|
|
||
|
|
ret = drm_panel_of_backlight(&lcd->panel);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
drm_panel_add(&lcd->panel);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void td028ttec1_remove(struct spi_device *spi)
|
||
|
|
{
|
||
|
|
struct td028ttec1_panel *lcd = spi_get_drvdata(spi);
|
||
|
|
|
||
|
|
drm_panel_remove(&lcd->panel);
|
||
|
|
drm_panel_disable(&lcd->panel);
|
||
|
|
drm_panel_unprepare(&lcd->panel);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id td028ttec1_of_match[] = {
|
||
|
|
{ .compatible = "tpo,td028ttec1", },
|
||
|
|
/* DT backward compatibility. */
|
||
|
|
{ .compatible = "toppoly,td028ttec1", },
|
||
|
|
{ /* sentinel */ },
|
||
|
|
};
|
||
|
|
|
||
|
|
MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
|
||
|
|
|
||
|
|
static const struct spi_device_id td028ttec1_ids[] = {
|
||
|
|
{ "td028ttec1", 0 },
|
||
|
|
{ /* sentinel */ }
|
||
|
|
};
|
||
|
|
|
||
|
|
MODULE_DEVICE_TABLE(spi, td028ttec1_ids);
|
||
|
|
|
||
|
|
static struct spi_driver td028ttec1_driver = {
|
||
|
|
.probe = td028ttec1_probe,
|
||
|
|
.remove = td028ttec1_remove,
|
||
|
|
.id_table = td028ttec1_ids,
|
||
|
|
.driver = {
|
||
|
|
.name = "panel-tpo-td028ttec1",
|
||
|
|
.of_match_table = td028ttec1_of_match,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
module_spi_driver(td028ttec1_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
|
||
|
|
MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
|
||
|
|
MODULE_LICENSE("GPL");
|