420 lines
12 KiB
C
420 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
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/* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */
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/* Copyright 2019 Collabora ltd. */
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#include <linux/bitfield.h>
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#include <linux/bitmap.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include "panfrost_device.h"
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#include "panfrost_features.h"
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#include "panfrost_issues.h"
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#include "panfrost_gpu.h"
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#include "panfrost_perfcnt.h"
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#include "panfrost_regs.h"
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static irqreturn_t panfrost_gpu_irq_handler(int irq, void *data)
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{
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struct panfrost_device *pfdev = data;
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u32 state = gpu_read(pfdev, GPU_INT_STAT);
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u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS);
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if (!state)
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return IRQ_NONE;
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if (state & GPU_IRQ_MASK_ERROR) {
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u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32;
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address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO);
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dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n",
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fault_status, panfrost_exception_name(fault_status & 0xFF),
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address);
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if (state & GPU_IRQ_MULTIPLE_FAULT)
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dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n");
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gpu_write(pfdev, GPU_INT_MASK, 0);
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}
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if (state & GPU_IRQ_PERFCNT_SAMPLE_COMPLETED)
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panfrost_perfcnt_sample_done(pfdev);
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if (state & GPU_IRQ_CLEAN_CACHES_COMPLETED)
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panfrost_perfcnt_clean_cache_done(pfdev);
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gpu_write(pfdev, GPU_INT_CLEAR, state);
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return IRQ_HANDLED;
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}
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int panfrost_gpu_soft_reset(struct panfrost_device *pfdev)
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{
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int ret;
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u32 val;
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gpu_write(pfdev, GPU_INT_MASK, 0);
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gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
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gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET);
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ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT,
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val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000);
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if (ret) {
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dev_err(pfdev->dev, "gpu soft reset timed out\n");
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return ret;
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}
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gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL);
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gpu_write(pfdev, GPU_INT_MASK, GPU_IRQ_MASK_ALL);
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return 0;
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}
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void panfrost_gpu_amlogic_quirk(struct panfrost_device *pfdev)
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{
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/*
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* The Amlogic integrated Mali-T820, Mali-G31 & Mali-G52 needs
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* these undocumented bits in GPU_PWR_OVERRIDE1 to be set in order
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* to operate correctly.
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*/
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gpu_write(pfdev, GPU_PWR_KEY, GPU_PWR_KEY_UNLOCK);
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gpu_write(pfdev, GPU_PWR_OVERRIDE1, 0xfff | (0x20 << 16));
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}
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static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev)
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{
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u32 quirks = 0;
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if (panfrost_has_hw_issue(pfdev, HW_ISSUE_8443) ||
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panfrost_has_hw_issue(pfdev, HW_ISSUE_11035))
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quirks |= SC_LS_PAUSEBUFFER_DISABLE;
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if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10327))
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quirks |= SC_SDC_DISABLE_OQ_DISCARD;
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if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10797))
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quirks |= SC_ENABLE_TEXGRD_FLAGS;
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if (!panfrost_has_hw_issue(pfdev, GPUCORE_1619)) {
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if (panfrost_model_cmp(pfdev, 0x750) < 0) /* T60x, T62x, T72x */
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quirks |= SC_LS_ATTR_CHECK_DISABLE;
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else if (panfrost_model_cmp(pfdev, 0x880) <= 0) /* T76x, T8xx */
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quirks |= SC_LS_ALLOW_ATTR_TYPES;
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}
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if (panfrost_has_hw_issue(pfdev, HW_ISSUE_TTRX_2968_TTRX_3162))
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quirks |= SC_VAR_ALGORITHM;
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if (panfrost_has_hw_feature(pfdev, HW_FEATURE_TLS_HASHING))
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quirks |= SC_TLS_HASH_ENABLE;
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if (quirks)
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gpu_write(pfdev, GPU_SHADER_CONFIG, quirks);
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quirks = gpu_read(pfdev, GPU_TILER_CONFIG);
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/* Set tiler clock gate override if required */
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if (panfrost_has_hw_issue(pfdev, HW_ISSUE_T76X_3953))
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quirks |= TC_CLOCK_GATE_OVERRIDE;
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gpu_write(pfdev, GPU_TILER_CONFIG, quirks);
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quirks = 0;
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if ((panfrost_model_eq(pfdev, 0x860) || panfrost_model_eq(pfdev, 0x880)) &&
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pfdev->features.revision >= 0x2000)
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quirks |= JM_MAX_JOB_THROTTLE_LIMIT << JM_JOB_THROTTLE_LIMIT_SHIFT;
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else if (panfrost_model_eq(pfdev, 0x6000) &&
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pfdev->features.coherency_features == COHERENCY_ACE)
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quirks |= (COHERENCY_ACE_LITE | COHERENCY_ACE) <<
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JM_FORCE_COHERENCY_FEATURES_SHIFT;
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if (panfrost_has_hw_feature(pfdev, HW_FEATURE_IDVS_GROUP_SIZE))
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quirks |= JM_DEFAULT_IDVS_GROUP_SIZE << JM_IDVS_GROUP_SIZE_SHIFT;
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if (quirks)
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gpu_write(pfdev, GPU_JM_CONFIG, quirks);
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/* Here goes platform specific quirks */
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if (pfdev->comp->vendor_quirk)
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pfdev->comp->vendor_quirk(pfdev);
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}
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#define MAX_HW_REVS 6
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struct panfrost_model {
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const char *name;
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u32 id;
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u32 id_mask;
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u64 features;
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u64 issues;
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struct {
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u32 revision;
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u64 issues;
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} revs[MAX_HW_REVS];
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};
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#define GPU_MODEL(_name, _id, ...) \
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{\
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.name = __stringify(_name), \
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.id = _id, \
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.features = hw_features_##_name, \
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.issues = hw_issues_##_name, \
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.revs = { __VA_ARGS__ }, \
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}
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#define GPU_REV_EXT(name, _rev, _p, _s, stat) \
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{\
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.revision = (_rev) << 12 | (_p) << 4 | (_s), \
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.issues = hw_issues_##name##_r##_rev##p##_p##stat, \
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}
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#define GPU_REV(name, r, p) GPU_REV_EXT(name, r, p, 0, )
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static const struct panfrost_model gpu_models[] = {
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/* T60x has an oddball version */
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GPU_MODEL(t600, 0x600,
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GPU_REV_EXT(t600, 0, 0, 1, _15dev0)),
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GPU_MODEL(t620, 0x620,
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GPU_REV(t620, 0, 1), GPU_REV(t620, 1, 0)),
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GPU_MODEL(t720, 0x720),
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GPU_MODEL(t760, 0x750,
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GPU_REV(t760, 0, 0), GPU_REV(t760, 0, 1),
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GPU_REV_EXT(t760, 0, 1, 0, _50rel0),
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GPU_REV(t760, 0, 2), GPU_REV(t760, 0, 3)),
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GPU_MODEL(t820, 0x820),
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GPU_MODEL(t830, 0x830),
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GPU_MODEL(t860, 0x860),
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GPU_MODEL(t880, 0x880),
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GPU_MODEL(g71, 0x6000,
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GPU_REV_EXT(g71, 0, 0, 1, _05dev0)),
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GPU_MODEL(g72, 0x6001),
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GPU_MODEL(g51, 0x7000),
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GPU_MODEL(g76, 0x7001),
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GPU_MODEL(g52, 0x7002),
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GPU_MODEL(g31, 0x7003,
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GPU_REV(g31, 1, 0)),
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GPU_MODEL(g57, 0x9001,
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GPU_REV(g57, 0, 0)),
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};
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static void panfrost_gpu_init_features(struct panfrost_device *pfdev)
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{
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u32 gpu_id, num_js, major, minor, status, rev;
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const char *name = "unknown";
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u64 hw_feat = 0;
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u64 hw_issues = hw_issues_all;
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const struct panfrost_model *model;
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int i;
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pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES);
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pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES);
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pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES);
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pfdev->features.mem_features = gpu_read(pfdev, GPU_MEM_FEATURES);
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pfdev->features.mmu_features = gpu_read(pfdev, GPU_MMU_FEATURES);
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pfdev->features.thread_features = gpu_read(pfdev, GPU_THREAD_FEATURES);
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pfdev->features.max_threads = gpu_read(pfdev, GPU_THREAD_MAX_THREADS);
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pfdev->features.thread_max_workgroup_sz = gpu_read(pfdev, GPU_THREAD_MAX_WORKGROUP_SIZE);
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pfdev->features.thread_max_barrier_sz = gpu_read(pfdev, GPU_THREAD_MAX_BARRIER_SIZE);
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pfdev->features.coherency_features = gpu_read(pfdev, GPU_COHERENCY_FEATURES);
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pfdev->features.afbc_features = gpu_read(pfdev, GPU_AFBC_FEATURES);
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for (i = 0; i < 4; i++)
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pfdev->features.texture_features[i] = gpu_read(pfdev, GPU_TEXTURE_FEATURES(i));
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pfdev->features.as_present = gpu_read(pfdev, GPU_AS_PRESENT);
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pfdev->features.js_present = gpu_read(pfdev, GPU_JS_PRESENT);
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num_js = hweight32(pfdev->features.js_present);
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for (i = 0; i < num_js; i++)
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pfdev->features.js_features[i] = gpu_read(pfdev, GPU_JS_FEATURES(i));
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pfdev->features.shader_present = gpu_read(pfdev, GPU_SHADER_PRESENT_LO);
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pfdev->features.shader_present |= (u64)gpu_read(pfdev, GPU_SHADER_PRESENT_HI) << 32;
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pfdev->features.tiler_present = gpu_read(pfdev, GPU_TILER_PRESENT_LO);
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pfdev->features.tiler_present |= (u64)gpu_read(pfdev, GPU_TILER_PRESENT_HI) << 32;
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pfdev->features.l2_present = gpu_read(pfdev, GPU_L2_PRESENT_LO);
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pfdev->features.l2_present |= (u64)gpu_read(pfdev, GPU_L2_PRESENT_HI) << 32;
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pfdev->features.nr_core_groups = hweight64(pfdev->features.l2_present);
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pfdev->features.stack_present = gpu_read(pfdev, GPU_STACK_PRESENT_LO);
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pfdev->features.stack_present |= (u64)gpu_read(pfdev, GPU_STACK_PRESENT_HI) << 32;
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pfdev->features.thread_tls_alloc = gpu_read(pfdev, GPU_THREAD_TLS_ALLOC);
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gpu_id = gpu_read(pfdev, GPU_ID);
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pfdev->features.revision = gpu_id & 0xffff;
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pfdev->features.id = gpu_id >> 16;
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/* The T60x has an oddball ID value. Fix it up to the standard Midgard
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* format so we (and userspace) don't have to special case it.
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*/
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if (pfdev->features.id == 0x6956)
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pfdev->features.id = 0x0600;
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major = (pfdev->features.revision >> 12) & 0xf;
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minor = (pfdev->features.revision >> 4) & 0xff;
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status = pfdev->features.revision & 0xf;
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rev = pfdev->features.revision;
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gpu_id = pfdev->features.id;
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for (model = gpu_models; model->name; model++) {
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int best = -1;
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if (!panfrost_model_eq(pfdev, model->id))
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continue;
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name = model->name;
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hw_feat = model->features;
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hw_issues |= model->issues;
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for (i = 0; i < MAX_HW_REVS; i++) {
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if (model->revs[i].revision == rev) {
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best = i;
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break;
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} else if (model->revs[i].revision == (rev & ~0xf))
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best = i;
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}
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if (best >= 0)
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hw_issues |= model->revs[best].issues;
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break;
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}
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bitmap_from_u64(pfdev->features.hw_features, hw_feat);
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bitmap_from_u64(pfdev->features.hw_issues, hw_issues);
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dev_info(pfdev->dev, "mali-%s id 0x%x major 0x%x minor 0x%x status 0x%x",
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name, gpu_id, major, minor, status);
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dev_info(pfdev->dev, "features: %64pb, issues: %64pb",
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pfdev->features.hw_features,
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pfdev->features.hw_issues);
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dev_info(pfdev->dev, "Features: L2:0x%08x Shader:0x%08x Tiler:0x%08x Mem:0x%0x MMU:0x%08x AS:0x%x JS:0x%x",
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pfdev->features.l2_features,
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pfdev->features.core_features,
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pfdev->features.tiler_features,
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pfdev->features.mem_features,
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pfdev->features.mmu_features,
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pfdev->features.as_present,
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pfdev->features.js_present);
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dev_info(pfdev->dev, "shader_present=0x%0llx l2_present=0x%0llx",
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pfdev->features.shader_present, pfdev->features.l2_present);
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}
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void panfrost_gpu_power_on(struct panfrost_device *pfdev)
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{
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int ret;
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u32 val;
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u64 core_mask = U64_MAX;
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panfrost_gpu_init_quirks(pfdev);
|
||
|
|
|
||
|
|
if (pfdev->features.l2_present != 1) {
|
||
|
|
/*
|
||
|
|
* Only support one core group now.
|
||
|
|
* ~(l2_present - 1) unsets all bits in l2_present except
|
||
|
|
* the bottom bit. (l2_present - 2) has all the bits in
|
||
|
|
* the first core group set. AND them together to generate
|
||
|
|
* a mask of cores in the first core group.
|
||
|
|
*/
|
||
|
|
core_mask = ~(pfdev->features.l2_present - 1) &
|
||
|
|
(pfdev->features.l2_present - 2);
|
||
|
|
dev_info_once(pfdev->dev, "using only 1st core group (%lu cores from %lu)\n",
|
||
|
|
hweight64(core_mask),
|
||
|
|
hweight64(pfdev->features.shader_present));
|
||
|
|
}
|
||
|
|
gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present & core_mask);
|
||
|
|
ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO,
|
||
|
|
val, val == (pfdev->features.l2_present & core_mask),
|
||
|
|
100, 20000);
|
||
|
|
if (ret)
|
||
|
|
dev_err(pfdev->dev, "error powering up gpu L2");
|
||
|
|
|
||
|
|
gpu_write(pfdev, SHADER_PWRON_LO,
|
||
|
|
pfdev->features.shader_present & core_mask);
|
||
|
|
ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO,
|
||
|
|
val, val == (pfdev->features.shader_present & core_mask),
|
||
|
|
100, 20000);
|
||
|
|
if (ret)
|
||
|
|
dev_err(pfdev->dev, "error powering up gpu shader");
|
||
|
|
|
||
|
|
gpu_write(pfdev, TILER_PWRON_LO, pfdev->features.tiler_present);
|
||
|
|
ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO,
|
||
|
|
val, val == pfdev->features.tiler_present, 100, 1000);
|
||
|
|
if (ret)
|
||
|
|
dev_err(pfdev->dev, "error powering up gpu tiler");
|
||
|
|
}
|
||
|
|
|
||
|
|
void panfrost_gpu_power_off(struct panfrost_device *pfdev)
|
||
|
|
{
|
||
|
|
gpu_write(pfdev, TILER_PWROFF_LO, 0);
|
||
|
|
gpu_write(pfdev, SHADER_PWROFF_LO, 0);
|
||
|
|
gpu_write(pfdev, L2_PWROFF_LO, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
int panfrost_gpu_init(struct panfrost_device *pfdev)
|
||
|
|
{
|
||
|
|
int err, irq;
|
||
|
|
|
||
|
|
err = panfrost_gpu_soft_reset(pfdev);
|
||
|
|
if (err)
|
||
|
|
return err;
|
||
|
|
|
||
|
|
panfrost_gpu_init_features(pfdev);
|
||
|
|
|
||
|
|
err = dma_set_mask_and_coherent(pfdev->dev,
|
||
|
|
DMA_BIT_MASK(FIELD_GET(0xff00, pfdev->features.mmu_features)));
|
||
|
|
if (err)
|
||
|
|
return err;
|
||
|
|
|
||
|
|
dma_set_max_seg_size(pfdev->dev, UINT_MAX);
|
||
|
|
|
||
|
|
irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "gpu");
|
||
|
|
if (irq <= 0)
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
err = devm_request_irq(pfdev->dev, irq, panfrost_gpu_irq_handler,
|
||
|
|
IRQF_SHARED, KBUILD_MODNAME "-gpu", pfdev);
|
||
|
|
if (err) {
|
||
|
|
dev_err(pfdev->dev, "failed to request gpu irq");
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
panfrost_gpu_power_on(pfdev);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void panfrost_gpu_fini(struct panfrost_device *pfdev)
|
||
|
|
{
|
||
|
|
panfrost_gpu_power_off(pfdev);
|
||
|
|
}
|
||
|
|
|
||
|
|
u32 panfrost_gpu_get_latest_flush_id(struct panfrost_device *pfdev)
|
||
|
|
{
|
||
|
|
u32 flush_id;
|
||
|
|
|
||
|
|
if (panfrost_has_hw_feature(pfdev, HW_FEATURE_FLUSH_REDUCTION)) {
|
||
|
|
/* Flush reduction only makes sense when the GPU is kept powered on between jobs */
|
||
|
|
if (pm_runtime_get_if_in_use(pfdev->dev)) {
|
||
|
|
flush_id = gpu_read(pfdev, GPU_LATEST_FLUSH_ID);
|
||
|
|
pm_runtime_put(pfdev->dev);
|
||
|
|
return flush_id;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|