478 lines
15 KiB
C
478 lines
15 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
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* Author:Mark Yao <mark.yao@rock-chips.com>
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*/
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#ifndef _ROCKCHIP_DRM_VOP2_H
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#define _ROCKCHIP_DRM_VOP2_H
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#include "rockchip_drm_vop.h"
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#include <linux/regmap.h>
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#include <drm/drm_modes.h>
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#define VOP_FEATURE_OUTPUT_10BIT BIT(0)
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#define WIN_FEATURE_AFBDC BIT(0)
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#define WIN_FEATURE_CLUSTER BIT(1)
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/*
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* the delay number of a window in different mode.
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*/
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enum win_dly_mode {
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VOP2_DLY_MODE_DEFAULT, /**< default mode */
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VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */
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VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */
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VOP2_DLY_MODE_MAX,
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};
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struct vop_rect {
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int width;
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int height;
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};
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enum vop2_scale_up_mode {
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VOP2_SCALE_UP_NRST_NBOR,
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VOP2_SCALE_UP_BIL,
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VOP2_SCALE_UP_BIC,
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};
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enum vop2_scale_down_mode {
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VOP2_SCALE_DOWN_NRST_NBOR,
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VOP2_SCALE_DOWN_BIL,
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VOP2_SCALE_DOWN_AVG,
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};
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enum vop2_win_regs {
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VOP2_WIN_ENABLE,
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VOP2_WIN_FORMAT,
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VOP2_WIN_CSC_MODE,
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VOP2_WIN_XMIRROR,
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VOP2_WIN_YMIRROR,
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VOP2_WIN_RB_SWAP,
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VOP2_WIN_UV_SWAP,
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VOP2_WIN_ACT_INFO,
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VOP2_WIN_DSP_INFO,
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VOP2_WIN_DSP_ST,
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VOP2_WIN_YRGB_MST,
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VOP2_WIN_UV_MST,
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VOP2_WIN_YRGB_VIR,
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VOP2_WIN_UV_VIR,
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VOP2_WIN_YUV_CLIP,
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VOP2_WIN_Y2R_EN,
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VOP2_WIN_R2Y_EN,
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VOP2_WIN_COLOR_KEY,
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VOP2_WIN_COLOR_KEY_EN,
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VOP2_WIN_DITHER_UP,
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/* scale regs */
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VOP2_WIN_SCALE_YRGB_X,
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VOP2_WIN_SCALE_YRGB_Y,
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VOP2_WIN_SCALE_CBCR_X,
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VOP2_WIN_SCALE_CBCR_Y,
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VOP2_WIN_YRGB_HOR_SCL_MODE,
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VOP2_WIN_YRGB_HSCL_FILTER_MODE,
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VOP2_WIN_YRGB_VER_SCL_MODE,
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VOP2_WIN_YRGB_VSCL_FILTER_MODE,
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VOP2_WIN_CBCR_VER_SCL_MODE,
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VOP2_WIN_CBCR_HSCL_FILTER_MODE,
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VOP2_WIN_CBCR_HOR_SCL_MODE,
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VOP2_WIN_CBCR_VSCL_FILTER_MODE,
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VOP2_WIN_VSD_CBCR_GT2,
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VOP2_WIN_VSD_CBCR_GT4,
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VOP2_WIN_VSD_YRGB_GT2,
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VOP2_WIN_VSD_YRGB_GT4,
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VOP2_WIN_BIC_COE_SEL,
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/* cluster regs */
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VOP2_WIN_CLUSTER_ENABLE,
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VOP2_WIN_AFBC_ENABLE,
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VOP2_WIN_CLUSTER_LB_MODE,
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/* afbc regs */
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VOP2_WIN_AFBC_FORMAT,
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VOP2_WIN_AFBC_RB_SWAP,
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VOP2_WIN_AFBC_UV_SWAP,
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VOP2_WIN_AFBC_AUTO_GATING_EN,
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VOP2_WIN_AFBC_BLOCK_SPLIT_EN,
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VOP2_WIN_AFBC_PIC_VIR_WIDTH,
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VOP2_WIN_AFBC_TILE_NUM,
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VOP2_WIN_AFBC_PIC_OFFSET,
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VOP2_WIN_AFBC_PIC_SIZE,
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VOP2_WIN_AFBC_DSP_OFFSET,
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VOP2_WIN_AFBC_TRANSFORM_OFFSET,
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VOP2_WIN_AFBC_HDR_PTR,
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VOP2_WIN_AFBC_HALF_BLOCK_EN,
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VOP2_WIN_AFBC_ROTATE_270,
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VOP2_WIN_AFBC_ROTATE_90,
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VOP2_WIN_MAX_REG,
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};
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struct vop2_win_data {
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const char *name;
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unsigned int phys_id;
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u32 base;
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enum drm_plane_type type;
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u32 nformats;
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const u32 *formats;
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const uint64_t *format_modifiers;
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const unsigned int supported_rotations;
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/**
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* @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2
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*/
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unsigned int layer_sel_id;
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uint64_t feature;
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unsigned int max_upscale_factor;
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unsigned int max_downscale_factor;
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const u8 dly[VOP2_DLY_MODE_MAX];
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};
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struct vop2_video_port_data {
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unsigned int id;
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u32 feature;
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u16 gamma_lut_len;
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u16 cubic_lut_len;
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struct vop_rect max_output;
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const u8 pre_scan_max_dly[4];
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const struct vop2_video_port_regs *regs;
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unsigned int offset;
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};
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struct vop2_data {
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u8 nr_vps;
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const struct vop2_ctrl *ctrl;
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const struct vop2_win_data *win;
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const struct vop2_video_port_data *vp;
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const struct vop_csc_table *csc_table;
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struct vop_rect max_input;
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struct vop_rect max_output;
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unsigned int win_size;
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unsigned int soc_id;
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};
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/* interrupt define */
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#define FS_NEW_INTR BIT(4)
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#define ADDR_SAME_INTR BIT(5)
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#define LINE_FLAG1_INTR BIT(6)
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#define WIN0_EMPTY_INTR BIT(7)
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#define WIN1_EMPTY_INTR BIT(8)
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#define WIN2_EMPTY_INTR BIT(9)
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#define WIN3_EMPTY_INTR BIT(10)
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#define HWC_EMPTY_INTR BIT(11)
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#define POST_BUF_EMPTY_INTR BIT(12)
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#define PWM_GEN_INTR BIT(13)
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#define DMA_FINISH_INTR BIT(14)
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#define FS_FIELD_INTR BIT(15)
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#define FE_INTR BIT(16)
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#define WB_UV_FIFO_FULL_INTR BIT(17)
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#define WB_YRGB_FIFO_FULL_INTR BIT(18)
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#define WB_COMPLETE_INTR BIT(19)
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/*
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* display output interface supported by rockchip lcdc
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*/
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#define ROCKCHIP_OUT_MODE_P888 0
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#define ROCKCHIP_OUT_MODE_BT1120 0
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#define ROCKCHIP_OUT_MODE_P666 1
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#define ROCKCHIP_OUT_MODE_P565 2
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#define ROCKCHIP_OUT_MODE_BT656 5
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#define ROCKCHIP_OUT_MODE_S888 8
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#define ROCKCHIP_OUT_MODE_S888_DUMMY 12
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#define ROCKCHIP_OUT_MODE_YUV420 14
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/* for use special outface */
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#define ROCKCHIP_OUT_MODE_AAAA 15
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enum vop_csc_format {
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CSC_BT601L,
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CSC_BT709L,
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CSC_BT601F,
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CSC_BT2020,
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};
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enum src_factor_mode {
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SRC_FAC_ALPHA_ZERO,
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SRC_FAC_ALPHA_ONE,
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SRC_FAC_ALPHA_DST,
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SRC_FAC_ALPHA_DST_INVERSE,
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SRC_FAC_ALPHA_SRC,
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SRC_FAC_ALPHA_SRC_GLOBAL,
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};
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enum dst_factor_mode {
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DST_FAC_ALPHA_ZERO,
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DST_FAC_ALPHA_ONE,
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DST_FAC_ALPHA_SRC,
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DST_FAC_ALPHA_SRC_INVERSE,
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DST_FAC_ALPHA_DST,
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DST_FAC_ALPHA_DST_GLOBAL,
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};
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#define RK3568_GRF_VO_CON1 0x0364
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/* System registers definition */
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#define RK3568_REG_CFG_DONE 0x000
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#define RK3568_VERSION_INFO 0x004
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#define RK3568_SYS_AUTO_GATING_CTRL 0x008
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#define RK3568_SYS_AXI_LUT_CTRL 0x024
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#define RK3568_DSP_IF_EN 0x028
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#define RK3568_DSP_IF_CTRL 0x02c
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#define RK3568_DSP_IF_POL 0x030
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#define RK3568_WB_CTRL 0x40
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#define RK3568_WB_XSCAL_FACTOR 0x44
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#define RK3568_WB_YRGB_MST 0x48
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#define RK3568_WB_CBR_MST 0x4C
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#define RK3568_OTP_WIN_EN 0x050
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#define RK3568_LUT_PORT_SEL 0x058
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#define RK3568_SYS_STATUS0 0x060
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#define RK3568_VP_LINE_FLAG(vp) (0x70 + (vp) * 0x4)
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#define RK3568_SYS0_INT_EN 0x80
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#define RK3568_SYS0_INT_CLR 0x84
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#define RK3568_SYS0_INT_STATUS 0x88
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#define RK3568_SYS1_INT_EN 0x90
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#define RK3568_SYS1_INT_CLR 0x94
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#define RK3568_SYS1_INT_STATUS 0x98
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#define RK3568_VP_INT_EN(vp) (0xA0 + (vp) * 0x10)
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#define RK3568_VP_INT_CLR(vp) (0xA4 + (vp) * 0x10)
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#define RK3568_VP_INT_STATUS(vp) (0xA8 + (vp) * 0x10)
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#define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10)
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/* Video Port registers definition */
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#define RK3568_VP_DSP_CTRL 0x00
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#define RK3568_VP_MIPI_CTRL 0x04
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#define RK3568_VP_COLOR_BAR_CTRL 0x08
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#define RK3568_VP_3D_LUT_CTRL 0x10
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#define RK3568_VP_3D_LUT_MST 0x20
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#define RK3568_VP_DSP_BG 0x2C
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#define RK3568_VP_PRE_SCAN_HTIMING 0x30
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#define RK3568_VP_POST_DSP_HACT_INFO 0x34
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#define RK3568_VP_POST_DSP_VACT_INFO 0x38
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#define RK3568_VP_POST_SCL_FACTOR_YRGB 0x3C
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#define RK3568_VP_POST_SCL_CTRL 0x40
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#define RK3568_VP_POST_DSP_VACT_INFO_F1 0x44
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#define RK3568_VP_DSP_HTOTAL_HS_END 0x48
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#define RK3568_VP_DSP_HACT_ST_END 0x4C
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#define RK3568_VP_DSP_VTOTAL_VS_END 0x50
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#define RK3568_VP_DSP_VACT_ST_END 0x54
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#define RK3568_VP_DSP_VS_ST_END_F1 0x58
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#define RK3568_VP_DSP_VACT_ST_END_F1 0x5C
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#define RK3568_VP_BCSH_CTRL 0x60
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#define RK3568_VP_BCSH_BCS 0x64
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#define RK3568_VP_BCSH_H 0x68
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#define RK3568_VP_BCSH_COLOR_BAR 0x6C
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/* Overlay registers definition */
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#define RK3568_OVL_CTRL 0x600
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#define RK3568_OVL_LAYER_SEL 0x604
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#define RK3568_OVL_PORT_SEL 0x608
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#define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610
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#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614
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#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618
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#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C
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#define RK3568_MIX0_SRC_COLOR_CTRL 0x650
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#define RK3568_MIX0_DST_COLOR_CTRL 0x654
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#define RK3568_MIX0_SRC_ALPHA_CTRL 0x658
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#define RK3568_MIX0_DST_ALPHA_CTRL 0x65C
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#define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0
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#define RK3568_HDR0_DST_COLOR_CTRL 0x6C4
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#define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8
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#define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC
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#define RK3568_VP_BG_MIX_CTRL(vp) (0x6E0 + (vp) * 4)
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#define RK3568_CLUSTER_DLY_NUM 0x6F0
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#define RK3568_SMART_DLY_NUM 0x6F8
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/* Cluster register definition, offset relative to window base */
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#define RK3568_CLUSTER_WIN_CTRL0 0x00
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#define RK3568_CLUSTER_WIN_CTRL1 0x04
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#define RK3568_CLUSTER_WIN_YRGB_MST 0x10
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#define RK3568_CLUSTER_WIN_CBR_MST 0x14
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#define RK3568_CLUSTER_WIN_VIR 0x18
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#define RK3568_CLUSTER_WIN_ACT_INFO 0x20
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#define RK3568_CLUSTER_WIN_DSP_INFO 0x24
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#define RK3568_CLUSTER_WIN_DSP_ST 0x28
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#define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB 0x30
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#define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET 0x3C
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#define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL 0x50
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#define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE 0x54
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#define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR 0x58
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#define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH 0x5C
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#define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE 0x60
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#define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64
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#define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET 0x68
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#define RK3568_CLUSTER_WIN_AFBCD_CTRL 0x6C
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#define RK3568_CLUSTER_CTRL 0x100
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/* (E)smart register definition, offset relative to window base */
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#define RK3568_SMART_CTRL0 0x00
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#define RK3568_SMART_CTRL1 0x04
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#define RK3568_SMART_REGION0_CTRL 0x10
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#define RK3568_SMART_REGION0_YRGB_MST 0x14
|
||
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#define RK3568_SMART_REGION0_CBR_MST 0x18
|
||
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#define RK3568_SMART_REGION0_VIR 0x1C
|
||
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#define RK3568_SMART_REGION0_ACT_INFO 0x20
|
||
|
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#define RK3568_SMART_REGION0_DSP_INFO 0x24
|
||
|
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#define RK3568_SMART_REGION0_DSP_ST 0x28
|
||
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#define RK3568_SMART_REGION0_SCL_CTRL 0x30
|
||
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#define RK3568_SMART_REGION0_SCL_FACTOR_YRGB 0x34
|
||
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#define RK3568_SMART_REGION0_SCL_FACTOR_CBR 0x38
|
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#define RK3568_SMART_REGION0_SCL_OFFSET 0x3C
|
||
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#define RK3568_SMART_REGION1_CTRL 0x40
|
||
|
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#define RK3568_SMART_REGION1_YRGB_MST 0x44
|
||
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#define RK3568_SMART_REGION1_CBR_MST 0x48
|
||
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#define RK3568_SMART_REGION1_VIR 0x4C
|
||
|
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#define RK3568_SMART_REGION1_ACT_INFO 0x50
|
||
|
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#define RK3568_SMART_REGION1_DSP_INFO 0x54
|
||
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#define RK3568_SMART_REGION1_DSP_ST 0x58
|
||
|
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#define RK3568_SMART_REGION1_SCL_CTRL 0x60
|
||
|
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#define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64
|
||
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#define RK3568_SMART_REGION1_SCL_FACTOR_CBR 0x68
|
||
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#define RK3568_SMART_REGION1_SCL_OFFSET 0x6C
|
||
|
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#define RK3568_SMART_REGION2_CTRL 0x70
|
||
|
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#define RK3568_SMART_REGION2_YRGB_MST 0x74
|
||
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#define RK3568_SMART_REGION2_CBR_MST 0x78
|
||
|
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#define RK3568_SMART_REGION2_VIR 0x7C
|
||
|
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#define RK3568_SMART_REGION2_ACT_INFO 0x80
|
||
|
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#define RK3568_SMART_REGION2_DSP_INFO 0x84
|
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|
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#define RK3568_SMART_REGION2_DSP_ST 0x88
|
||
|
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#define RK3568_SMART_REGION2_SCL_CTRL 0x90
|
||
|
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#define RK3568_SMART_REGION2_SCL_FACTOR_YRGB 0x94
|
||
|
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#define RK3568_SMART_REGION2_SCL_FACTOR_CBR 0x98
|
||
|
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#define RK3568_SMART_REGION2_SCL_OFFSET 0x9C
|
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#define RK3568_SMART_REGION3_CTRL 0xA0
|
||
|
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#define RK3568_SMART_REGION3_YRGB_MST 0xA4
|
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#define RK3568_SMART_REGION3_CBR_MST 0xA8
|
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|
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#define RK3568_SMART_REGION3_VIR 0xAC
|
||
|
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#define RK3568_SMART_REGION3_ACT_INFO 0xB0
|
||
|
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#define RK3568_SMART_REGION3_DSP_INFO 0xB4
|
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|
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#define RK3568_SMART_REGION3_DSP_ST 0xB8
|
||
|
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#define RK3568_SMART_REGION3_SCL_CTRL 0xC0
|
||
|
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#define RK3568_SMART_REGION3_SCL_FACTOR_YRGB 0xC4
|
||
|
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#define RK3568_SMART_REGION3_SCL_FACTOR_CBR 0xC8
|
||
|
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#define RK3568_SMART_REGION3_SCL_OFFSET 0xCC
|
||
|
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#define RK3568_SMART_COLOR_KEY_CTRL 0xD0
|
||
|
|
|
||
|
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/* HDR register definition */
|
||
|
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#define RK3568_HDR_LUT_CTRL 0x2000
|
||
|
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#define RK3568_HDR_LUT_MST 0x2004
|
||
|
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#define RK3568_SDR2HDR_CTRL 0x2010
|
||
|
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#define RK3568_HDR2SDR_CTRL 0x2020
|
||
|
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#define RK3568_HDR2SDR_SRC_RANGE 0x2024
|
||
|
|
#define RK3568_HDR2SDR_NORMFACEETF 0x2028
|
||
|
|
#define RK3568_HDR2SDR_DST_RANGE 0x202C
|
||
|
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#define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030
|
||
|
|
#define RK3568_HDR_EETF_OETF_Y0 0x203C
|
||
|
|
#define RK3568_HDR_SAT_Y0 0x20C0
|
||
|
|
#define RK3568_HDR_EOTF_OETF_Y0 0x20F0
|
||
|
|
#define RK3568_HDR_OETF_DX_POW1 0x2200
|
||
|
|
#define RK3568_HDR_OETF_XN1 0x2300
|
||
|
|
|
||
|
|
#define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN BIT(15)
|
||
|
|
|
||
|
|
#define RK3568_VP_DSP_CTRL__STANDBY BIT(31)
|
||
|
|
#define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE BIT(20)
|
||
|
|
#define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL GENMASK(19, 18)
|
||
|
|
#define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN BIT(17)
|
||
|
|
#define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN BIT(16)
|
||
|
|
#define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y BIT(15)
|
||
|
|
#define RK3568_VP_DSP_CTRL__DSP_RB_SWAP BIT(9)
|
||
|
|
#define RK3568_VP_DSP_CTRL__DSP_INTERLACE BIT(7)
|
||
|
|
#define RK3568_VP_DSP_CTRL__DSP_FILED_POL BIT(6)
|
||
|
|
#define RK3568_VP_DSP_CTRL__P2I_EN BIT(5)
|
||
|
|
#define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV BIT(4)
|
||
|
|
#define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0)
|
||
|
|
|
||
|
|
#define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1)
|
||
|
|
#define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0)
|
||
|
|
|
||
|
|
#define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX GENMASK(26, 25)
|
||
|
|
#define RK3568_SYS_DSP_INFACE_EN_LVDS1 BIT(24)
|
||
|
|
#define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21)
|
||
|
|
#define RK3568_SYS_DSP_INFACE_EN_MIPI1 BIT(20)
|
||
|
|
#define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX GENMASK(19, 18)
|
||
|
|
#define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(17, 16)
|
||
|
|
#define RK3568_SYS_DSP_INFACE_EN_EDP_MUX GENMASK(15, 14)
|
||
|
|
#define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX GENMASK(11, 10)
|
||
|
|
#define RK3568_SYS_DSP_INFACE_EN_RGB_MUX GENMASK(9, 8)
|
||
|
|
#define RK3568_SYS_DSP_INFACE_EN_LVDS0 BIT(5)
|
||
|
|
#define RK3568_SYS_DSP_INFACE_EN_MIPI0 BIT(4)
|
||
|
|
#define RK3568_SYS_DSP_INFACE_EN_EDP BIT(3)
|
||
|
|
#define RK3568_SYS_DSP_INFACE_EN_HDMI BIT(1)
|
||
|
|
#define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0)
|
||
|
|
|
||
|
|
#define RK3568_DSP_IF_POL__MIPI_PIN_POL GENMASK(19, 16)
|
||
|
|
#define RK3568_DSP_IF_POL__EDP_PIN_POL GENMASK(15, 12)
|
||
|
|
#define RK3568_DSP_IF_POL__HDMI_PIN_POL GENMASK(7, 4)
|
||
|
|
#define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0)
|
||
|
|
|
||
|
|
#define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK BIT(5)
|
||
|
|
#define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 BIT(4)
|
||
|
|
|
||
|
|
#define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN BIT(31)
|
||
|
|
|
||
|
|
#define RK3568_DSP_IF_POL__CFG_DONE_IMD BIT(28)
|
||
|
|
|
||
|
|
#define VOP2_SYS_AXI_BUS_NUM 2
|
||
|
|
|
||
|
|
#define VOP2_CLUSTER_YUV444_10 0x12
|
||
|
|
|
||
|
|
#define VOP2_COLOR_KEY_MASK BIT(31)
|
||
|
|
|
||
|
|
#define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28)
|
||
|
|
|
||
|
|
#define RK3568_VP_BG_MIX_CTRL__BG_DLY GENMASK(31, 24)
|
||
|
|
|
||
|
|
#define RK3568_OVL_PORT_SEL__SEL_PORT GENMASK(31, 16)
|
||
|
|
#define RK3568_OVL_PORT_SEL__SMART1 GENMASK(31, 30)
|
||
|
|
#define RK3568_OVL_PORT_SEL__SMART0 GENMASK(29, 28)
|
||
|
|
#define RK3568_OVL_PORT_SEL__ESMART1 GENMASK(27, 26)
|
||
|
|
#define RK3568_OVL_PORT_SEL__ESMART0 GENMASK(25, 24)
|
||
|
|
#define RK3568_OVL_PORT_SEL__CLUSTER1 GENMASK(19, 18)
|
||
|
|
#define RK3568_OVL_PORT_SEL__CLUSTER0 GENMASK(17, 16)
|
||
|
|
#define RK3568_OVL_PORT_SET__PORT2_MUX GENMASK(11, 8)
|
||
|
|
#define RK3568_OVL_PORT_SET__PORT1_MUX GENMASK(7, 4)
|
||
|
|
#define RK3568_OVL_PORT_SET__PORT0_MUX GENMASK(3, 0)
|
||
|
|
#define RK3568_OVL_LAYER_SEL__LAYER(layer, x) ((x) << ((layer) * 4))
|
||
|
|
|
||
|
|
#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1 GENMASK(31, 24)
|
||
|
|
#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0 GENMASK(23, 16)
|
||
|
|
#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1 GENMASK(15, 8)
|
||
|
|
#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0)
|
||
|
|
|
||
|
|
#define RK3568_SMART_DLY_NUM__SMART1 GENMASK(31, 24)
|
||
|
|
#define RK3568_SMART_DLY_NUM__SMART0 GENMASK(23, 16)
|
||
|
|
#define RK3568_SMART_DLY_NUM__ESMART1 GENMASK(15, 8)
|
||
|
|
#define RK3568_SMART_DLY_NUM__ESMART0 GENMASK(7, 0)
|
||
|
|
|
||
|
|
#define VP_INT_DSP_HOLD_VALID BIT(6)
|
||
|
|
#define VP_INT_FS_FIELD BIT(5)
|
||
|
|
#define VP_INT_POST_BUF_EMPTY BIT(4)
|
||
|
|
#define VP_INT_LINE_FLAG1 BIT(3)
|
||
|
|
#define VP_INT_LINE_FLAG0 BIT(2)
|
||
|
|
#define VOP2_INT_BUS_ERRPR BIT(1)
|
||
|
|
#define VP_INT_FS BIT(0)
|
||
|
|
|
||
|
|
#define POLFLAG_DCLK_INV BIT(3)
|
||
|
|
|
||
|
|
enum vop2_layer_phy_id {
|
||
|
|
ROCKCHIP_VOP2_CLUSTER0 = 0,
|
||
|
|
ROCKCHIP_VOP2_CLUSTER1,
|
||
|
|
ROCKCHIP_VOP2_ESMART0,
|
||
|
|
ROCKCHIP_VOP2_ESMART1,
|
||
|
|
ROCKCHIP_VOP2_SMART0,
|
||
|
|
ROCKCHIP_VOP2_SMART1,
|
||
|
|
ROCKCHIP_VOP2_CLUSTER2,
|
||
|
|
ROCKCHIP_VOP2_CLUSTER3,
|
||
|
|
ROCKCHIP_VOP2_ESMART2,
|
||
|
|
ROCKCHIP_VOP2_ESMART3,
|
||
|
|
ROCKCHIP_VOP2_PHY_ID_INVALID = -1,
|
||
|
|
};
|
||
|
|
|
||
|
|
extern const struct component_ops vop2_component_ops;
|
||
|
|
|
||
|
|
#endif /* _ROCKCHIP_DRM_VOP2_H */
|