399 lines
14 KiB
C
399 lines
14 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2020 Invensense, Inc.
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*/
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#ifndef INV_ICM42600_H_
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#define INV_ICM42600_H_
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/regmap.h>
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#include <linux/mutex.h>
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#include <linux/regulator/consumer.h>
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#include <linux/pm.h>
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#include <linux/iio/iio.h>
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#include "inv_icm42600_buffer.h"
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enum inv_icm42600_chip {
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INV_CHIP_INVALID,
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INV_CHIP_ICM42600,
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INV_CHIP_ICM42602,
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INV_CHIP_ICM42605,
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INV_CHIP_ICM42622,
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INV_CHIP_ICM42631,
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INV_CHIP_NB,
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};
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/* serial bus slew rates */
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enum inv_icm42600_slew_rate {
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INV_ICM42600_SLEW_RATE_20_60NS,
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INV_ICM42600_SLEW_RATE_12_36NS,
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INV_ICM42600_SLEW_RATE_6_18NS,
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INV_ICM42600_SLEW_RATE_4_12NS,
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INV_ICM42600_SLEW_RATE_2_6NS,
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INV_ICM42600_SLEW_RATE_INF_2NS,
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};
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enum inv_icm42600_sensor_mode {
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INV_ICM42600_SENSOR_MODE_OFF,
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INV_ICM42600_SENSOR_MODE_STANDBY,
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INV_ICM42600_SENSOR_MODE_LOW_POWER,
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INV_ICM42600_SENSOR_MODE_LOW_NOISE,
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INV_ICM42600_SENSOR_MODE_NB,
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};
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/* gyroscope fullscale values */
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enum inv_icm42600_gyro_fs {
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INV_ICM42600_GYRO_FS_2000DPS,
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INV_ICM42600_GYRO_FS_1000DPS,
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INV_ICM42600_GYRO_FS_500DPS,
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INV_ICM42600_GYRO_FS_250DPS,
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INV_ICM42600_GYRO_FS_125DPS,
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INV_ICM42600_GYRO_FS_62_5DPS,
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INV_ICM42600_GYRO_FS_31_25DPS,
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INV_ICM42600_GYRO_FS_15_625DPS,
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INV_ICM42600_GYRO_FS_NB,
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};
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/* accelerometer fullscale values */
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enum inv_icm42600_accel_fs {
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INV_ICM42600_ACCEL_FS_16G,
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INV_ICM42600_ACCEL_FS_8G,
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INV_ICM42600_ACCEL_FS_4G,
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INV_ICM42600_ACCEL_FS_2G,
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INV_ICM42600_ACCEL_FS_NB,
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};
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/* ODR suffixed by LN or LP are Low-Noise or Low-Power mode only */
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enum inv_icm42600_odr {
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INV_ICM42600_ODR_8KHZ_LN = 3,
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INV_ICM42600_ODR_4KHZ_LN,
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INV_ICM42600_ODR_2KHZ_LN,
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INV_ICM42600_ODR_1KHZ_LN,
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INV_ICM42600_ODR_200HZ,
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INV_ICM42600_ODR_100HZ,
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INV_ICM42600_ODR_50HZ,
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INV_ICM42600_ODR_25HZ,
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INV_ICM42600_ODR_12_5HZ,
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INV_ICM42600_ODR_6_25HZ_LP,
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INV_ICM42600_ODR_3_125HZ_LP,
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INV_ICM42600_ODR_1_5625HZ_LP,
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INV_ICM42600_ODR_500HZ,
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INV_ICM42600_ODR_NB,
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};
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enum inv_icm42600_filter {
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/* Low-Noise mode sensor data filter (3rd order filter by default) */
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INV_ICM42600_FILTER_BW_ODR_DIV_2,
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/* Low-Power mode sensor data filter (averaging) */
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INV_ICM42600_FILTER_AVG_1X = 1,
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INV_ICM42600_FILTER_AVG_16X = 6,
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};
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struct inv_icm42600_sensor_conf {
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int mode;
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int fs;
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int odr;
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int filter;
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};
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#define INV_ICM42600_SENSOR_CONF_INIT {-1, -1, -1, -1}
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struct inv_icm42600_conf {
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struct inv_icm42600_sensor_conf gyro;
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struct inv_icm42600_sensor_conf accel;
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bool temp_en;
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};
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struct inv_icm42600_suspended {
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enum inv_icm42600_sensor_mode gyro;
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enum inv_icm42600_sensor_mode accel;
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bool temp;
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};
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/**
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* struct inv_icm42600_state - driver state variables
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* @lock: lock for serializing multiple registers access.
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* @chip: chip identifier.
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* @name: chip name.
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* @map: regmap pointer.
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* @vdd_supply: VDD voltage regulator for the chip.
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* @vddio_supply: I/O voltage regulator for the chip.
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* @orientation: sensor chip orientation relative to main hardware.
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* @conf: chip sensors configurations.
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* @suspended: suspended sensors configuration.
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* @indio_gyro: gyroscope IIO device.
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* @indio_accel: accelerometer IIO device.
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* @buffer: data transfer buffer aligned for DMA.
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* @fifo: FIFO management structure.
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* @timestamp: interrupt timestamps.
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*/
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struct inv_icm42600_state {
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struct mutex lock;
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enum inv_icm42600_chip chip;
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const char *name;
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struct regmap *map;
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struct regulator *vdd_supply;
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struct regulator *vddio_supply;
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struct iio_mount_matrix orientation;
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struct inv_icm42600_conf conf;
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struct inv_icm42600_suspended suspended;
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struct iio_dev *indio_gyro;
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struct iio_dev *indio_accel;
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uint8_t buffer[2] __aligned(IIO_DMA_MINALIGN);
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struct inv_icm42600_fifo fifo;
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struct {
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int64_t gyro;
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int64_t accel;
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} timestamp;
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};
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/* Virtual register addresses: @bank on MSB (4 upper bits), @address on LSB */
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/* Bank selection register, available in all banks */
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#define INV_ICM42600_REG_BANK_SEL 0x76
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#define INV_ICM42600_BANK_SEL_MASK GENMASK(2, 0)
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/* User bank 0 (MSB 0x00) */
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#define INV_ICM42600_REG_DEVICE_CONFIG 0x0011
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#define INV_ICM42600_DEVICE_CONFIG_SOFT_RESET BIT(0)
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#define INV_ICM42600_REG_DRIVE_CONFIG 0x0013
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#define INV_ICM42600_DRIVE_CONFIG_I2C_MASK GENMASK(5, 3)
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#define INV_ICM42600_DRIVE_CONFIG_I2C(_rate) \
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FIELD_PREP(INV_ICM42600_DRIVE_CONFIG_I2C_MASK, (_rate))
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#define INV_ICM42600_DRIVE_CONFIG_SPI_MASK GENMASK(2, 0)
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#define INV_ICM42600_DRIVE_CONFIG_SPI(_rate) \
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FIELD_PREP(INV_ICM42600_DRIVE_CONFIG_SPI_MASK, (_rate))
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#define INV_ICM42600_REG_INT_CONFIG 0x0014
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#define INV_ICM42600_INT_CONFIG_INT2_LATCHED BIT(5)
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#define INV_ICM42600_INT_CONFIG_INT2_PUSH_PULL BIT(4)
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#define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_HIGH BIT(3)
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#define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_LOW 0x00
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#define INV_ICM42600_INT_CONFIG_INT1_LATCHED BIT(2)
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#define INV_ICM42600_INT_CONFIG_INT1_PUSH_PULL BIT(1)
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#define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_HIGH BIT(0)
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#define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_LOW 0x00
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#define INV_ICM42600_REG_FIFO_CONFIG 0x0016
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#define INV_ICM42600_FIFO_CONFIG_MASK GENMASK(7, 6)
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#define INV_ICM42600_FIFO_CONFIG_BYPASS \
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FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 0)
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#define INV_ICM42600_FIFO_CONFIG_STREAM \
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FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 1)
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#define INV_ICM42600_FIFO_CONFIG_STOP_ON_FULL \
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FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 2)
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/* all sensor data are 16 bits (2 registers wide) in big-endian */
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#define INV_ICM42600_REG_TEMP_DATA 0x001D
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#define INV_ICM42600_REG_ACCEL_DATA_X 0x001F
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#define INV_ICM42600_REG_ACCEL_DATA_Y 0x0021
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#define INV_ICM42600_REG_ACCEL_DATA_Z 0x0023
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#define INV_ICM42600_REG_GYRO_DATA_X 0x0025
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#define INV_ICM42600_REG_GYRO_DATA_Y 0x0027
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#define INV_ICM42600_REG_GYRO_DATA_Z 0x0029
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#define INV_ICM42600_DATA_INVALID -32768
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#define INV_ICM42600_REG_INT_STATUS 0x002D
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#define INV_ICM42600_INT_STATUS_UI_FSYNC BIT(6)
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#define INV_ICM42600_INT_STATUS_PLL_RDY BIT(5)
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#define INV_ICM42600_INT_STATUS_RESET_DONE BIT(4)
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#define INV_ICM42600_INT_STATUS_DATA_RDY BIT(3)
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#define INV_ICM42600_INT_STATUS_FIFO_THS BIT(2)
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#define INV_ICM42600_INT_STATUS_FIFO_FULL BIT(1)
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#define INV_ICM42600_INT_STATUS_AGC_RDY BIT(0)
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/*
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* FIFO access registers
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* FIFO count is 16 bits (2 registers) big-endian
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* FIFO data is a continuous read register to read FIFO content
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*/
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#define INV_ICM42600_REG_FIFO_COUNT 0x002E
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#define INV_ICM42600_REG_FIFO_DATA 0x0030
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#define INV_ICM42600_REG_SIGNAL_PATH_RESET 0x004B
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#define INV_ICM42600_SIGNAL_PATH_RESET_DMP_INIT_EN BIT(6)
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#define INV_ICM42600_SIGNAL_PATH_RESET_DMP_MEM_RESET BIT(5)
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#define INV_ICM42600_SIGNAL_PATH_RESET_RESET BIT(3)
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#define INV_ICM42600_SIGNAL_PATH_RESET_TMST_STROBE BIT(2)
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#define INV_ICM42600_SIGNAL_PATH_RESET_FIFO_FLUSH BIT(1)
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/* default configuration: all data big-endian and fifo count in bytes */
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#define INV_ICM42600_REG_INTF_CONFIG0 0x004C
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#define INV_ICM42600_INTF_CONFIG0_FIFO_HOLD_LAST_DATA BIT(7)
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#define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_REC BIT(6)
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#define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_ENDIAN BIT(5)
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#define INV_ICM42600_INTF_CONFIG0_SENSOR_DATA_ENDIAN BIT(4)
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#define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK GENMASK(1, 0)
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#define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_SPI_DIS \
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FIELD_PREP(INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK, 2)
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#define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_I2C_DIS \
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FIELD_PREP(INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK, 3)
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#define INV_ICM42600_REG_INTF_CONFIG1 0x004D
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#define INV_ICM42600_INTF_CONFIG1_ACCEL_LP_CLK_RC BIT(3)
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#define INV_ICM42600_REG_PWR_MGMT0 0x004E
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#define INV_ICM42600_PWR_MGMT0_TEMP_DIS BIT(5)
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#define INV_ICM42600_PWR_MGMT0_IDLE BIT(4)
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#define INV_ICM42600_PWR_MGMT0_GYRO(_mode) \
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FIELD_PREP(GENMASK(3, 2), (_mode))
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#define INV_ICM42600_PWR_MGMT0_ACCEL(_mode) \
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FIELD_PREP(GENMASK(1, 0), (_mode))
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#define INV_ICM42600_REG_GYRO_CONFIG0 0x004F
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#define INV_ICM42600_GYRO_CONFIG0_FS(_fs) \
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FIELD_PREP(GENMASK(7, 5), (_fs))
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#define INV_ICM42600_GYRO_CONFIG0_ODR(_odr) \
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FIELD_PREP(GENMASK(3, 0), (_odr))
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#define INV_ICM42600_REG_ACCEL_CONFIG0 0x0050
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#define INV_ICM42600_ACCEL_CONFIG0_FS(_fs) \
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FIELD_PREP(GENMASK(7, 5), (_fs))
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#define INV_ICM42600_ACCEL_CONFIG0_ODR(_odr) \
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FIELD_PREP(GENMASK(3, 0), (_odr))
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#define INV_ICM42600_REG_GYRO_ACCEL_CONFIG0 0x0052
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#define INV_ICM42600_GYRO_ACCEL_CONFIG0_ACCEL_FILT(_f) \
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FIELD_PREP(GENMASK(7, 4), (_f))
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#define INV_ICM42600_GYRO_ACCEL_CONFIG0_GYRO_FILT(_f) \
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FIELD_PREP(GENMASK(3, 0), (_f))
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#define INV_ICM42600_REG_TMST_CONFIG 0x0054
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#define INV_ICM42600_TMST_CONFIG_MASK GENMASK(4, 0)
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#define INV_ICM42600_TMST_CONFIG_TMST_TO_REGS_EN BIT(4)
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#define INV_ICM42600_TMST_CONFIG_TMST_RES_16US BIT(3)
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#define INV_ICM42600_TMST_CONFIG_TMST_DELTA_EN BIT(2)
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#define INV_ICM42600_TMST_CONFIG_TMST_FSYNC_EN BIT(1)
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#define INV_ICM42600_TMST_CONFIG_TMST_EN BIT(0)
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#define INV_ICM42600_REG_FIFO_CONFIG1 0x005F
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#define INV_ICM42600_FIFO_CONFIG1_RESUME_PARTIAL_RD BIT(6)
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#define INV_ICM42600_FIFO_CONFIG1_WM_GT_TH BIT(5)
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#define INV_ICM42600_FIFO_CONFIG1_TMST_FSYNC_EN BIT(3)
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#define INV_ICM42600_FIFO_CONFIG1_TEMP_EN BIT(2)
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#define INV_ICM42600_FIFO_CONFIG1_GYRO_EN BIT(1)
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#define INV_ICM42600_FIFO_CONFIG1_ACCEL_EN BIT(0)
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/* FIFO watermark is 16 bits (2 registers wide) in little-endian */
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#define INV_ICM42600_REG_FIFO_WATERMARK 0x0060
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#define INV_ICM42600_FIFO_WATERMARK_VAL(_wm) \
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cpu_to_le16((_wm) & GENMASK(11, 0))
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/* FIFO is 2048 bytes, let 12 samples for reading latency */
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#define INV_ICM42600_FIFO_WATERMARK_MAX (2048 - 12 * 16)
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#define INV_ICM42600_REG_INT_CONFIG1 0x0064
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#define INV_ICM42600_INT_CONFIG1_TPULSE_DURATION BIT(6)
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#define INV_ICM42600_INT_CONFIG1_TDEASSERT_DISABLE BIT(5)
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#define INV_ICM42600_INT_CONFIG1_ASYNC_RESET BIT(4)
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#define INV_ICM42600_REG_INT_SOURCE0 0x0065
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#define INV_ICM42600_INT_SOURCE0_UI_FSYNC_INT1_EN BIT(6)
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#define INV_ICM42600_INT_SOURCE0_PLL_RDY_INT1_EN BIT(5)
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#define INV_ICM42600_INT_SOURCE0_RESET_DONE_INT1_EN BIT(4)
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#define INV_ICM42600_INT_SOURCE0_UI_DRDY_INT1_EN BIT(3)
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#define INV_ICM42600_INT_SOURCE0_FIFO_THS_INT1_EN BIT(2)
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#define INV_ICM42600_INT_SOURCE0_FIFO_FULL_INT1_EN BIT(1)
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#define INV_ICM42600_INT_SOURCE0_UI_AGC_RDY_INT1_EN BIT(0)
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#define INV_ICM42600_REG_WHOAMI 0x0075
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#define INV_ICM42600_WHOAMI_ICM42600 0x40
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#define INV_ICM42600_WHOAMI_ICM42602 0x41
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#define INV_ICM42600_WHOAMI_ICM42605 0x42
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#define INV_ICM42600_WHOAMI_ICM42622 0x46
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#define INV_ICM42600_WHOAMI_ICM42631 0x5C
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/* User bank 1 (MSB 0x10) */
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#define INV_ICM42600_REG_SENSOR_CONFIG0 0x1003
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#define INV_ICM42600_SENSOR_CONFIG0_ZG_DISABLE BIT(5)
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#define INV_ICM42600_SENSOR_CONFIG0_YG_DISABLE BIT(4)
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#define INV_ICM42600_SENSOR_CONFIG0_XG_DISABLE BIT(3)
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#define INV_ICM42600_SENSOR_CONFIG0_ZA_DISABLE BIT(2)
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#define INV_ICM42600_SENSOR_CONFIG0_YA_DISABLE BIT(1)
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#define INV_ICM42600_SENSOR_CONFIG0_XA_DISABLE BIT(0)
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/* Timestamp value is 20 bits (3 registers) in little-endian */
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#define INV_ICM42600_REG_TMSTVAL 0x1062
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#define INV_ICM42600_TMSTVAL_MASK GENMASK(19, 0)
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#define INV_ICM42600_REG_INTF_CONFIG4 0x107A
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#define INV_ICM42600_INTF_CONFIG4_I3C_BUS_ONLY BIT(6)
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#define INV_ICM42600_INTF_CONFIG4_SPI_AP_4WIRE BIT(1)
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#define INV_ICM42600_REG_INTF_CONFIG6 0x107C
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#define INV_ICM42600_INTF_CONFIG6_MASK GENMASK(4, 0)
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#define INV_ICM42600_INTF_CONFIG6_I3C_EN BIT(4)
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#define INV_ICM42600_INTF_CONFIG6_I3C_IBI_BYTE_EN BIT(3)
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#define INV_ICM42600_INTF_CONFIG6_I3C_IBI_EN BIT(2)
|
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#define INV_ICM42600_INTF_CONFIG6_I3C_DDR_EN BIT(1)
|
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#define INV_ICM42600_INTF_CONFIG6_I3C_SDR_EN BIT(0)
|
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/* User bank 4 (MSB 0x40) */
|
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#define INV_ICM42600_REG_INT_SOURCE8 0x404F
|
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#define INV_ICM42600_INT_SOURCE8_FSYNC_IBI_EN BIT(5)
|
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#define INV_ICM42600_INT_SOURCE8_PLL_RDY_IBI_EN BIT(4)
|
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|
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#define INV_ICM42600_INT_SOURCE8_UI_DRDY_IBI_EN BIT(3)
|
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|
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#define INV_ICM42600_INT_SOURCE8_FIFO_THS_IBI_EN BIT(2)
|
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|
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#define INV_ICM42600_INT_SOURCE8_FIFO_FULL_IBI_EN BIT(1)
|
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|
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#define INV_ICM42600_INT_SOURCE8_AGC_RDY_IBI_EN BIT(0)
|
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|
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|
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#define INV_ICM42600_REG_OFFSET_USER0 0x4077
|
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|
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#define INV_ICM42600_REG_OFFSET_USER1 0x4078
|
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|
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#define INV_ICM42600_REG_OFFSET_USER2 0x4079
|
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|
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#define INV_ICM42600_REG_OFFSET_USER3 0x407A
|
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|
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#define INV_ICM42600_REG_OFFSET_USER4 0x407B
|
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|
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#define INV_ICM42600_REG_OFFSET_USER5 0x407C
|
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|
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#define INV_ICM42600_REG_OFFSET_USER6 0x407D
|
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|
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#define INV_ICM42600_REG_OFFSET_USER7 0x407E
|
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|
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#define INV_ICM42600_REG_OFFSET_USER8 0x407F
|
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|
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|
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|
|
/* Sleep times required by the driver */
|
||
|
|
#define INV_ICM42600_POWER_UP_TIME_MS 100
|
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|
|
#define INV_ICM42600_RESET_TIME_MS 1
|
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|
|
#define INV_ICM42600_ACCEL_STARTUP_TIME_MS 20
|
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|
|
#define INV_ICM42600_GYRO_STARTUP_TIME_MS 60
|
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|
|
#define INV_ICM42600_GYRO_STOP_TIME_MS 150
|
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|
|
#define INV_ICM42600_TEMP_STARTUP_TIME_MS 14
|
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|
|
#define INV_ICM42600_SUSPEND_DELAY_MS 2000
|
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|
|
|
||
|
|
typedef int (*inv_icm42600_bus_setup)(struct inv_icm42600_state *);
|
||
|
|
|
||
|
|
extern const struct regmap_config inv_icm42600_regmap_config;
|
||
|
|
extern const struct dev_pm_ops inv_icm42600_pm_ops;
|
||
|
|
|
||
|
|
const struct iio_mount_matrix *
|
||
|
|
inv_icm42600_get_mount_matrix(const struct iio_dev *indio_dev,
|
||
|
|
const struct iio_chan_spec *chan);
|
||
|
|
|
||
|
|
uint32_t inv_icm42600_odr_to_period(enum inv_icm42600_odr odr);
|
||
|
|
|
||
|
|
int inv_icm42600_set_accel_conf(struct inv_icm42600_state *st,
|
||
|
|
struct inv_icm42600_sensor_conf *conf,
|
||
|
|
unsigned int *sleep_ms);
|
||
|
|
|
||
|
|
int inv_icm42600_set_gyro_conf(struct inv_icm42600_state *st,
|
||
|
|
struct inv_icm42600_sensor_conf *conf,
|
||
|
|
unsigned int *sleep_ms);
|
||
|
|
|
||
|
|
int inv_icm42600_set_temp_conf(struct inv_icm42600_state *st, bool enable,
|
||
|
|
unsigned int *sleep_ms);
|
||
|
|
|
||
|
|
int inv_icm42600_debugfs_reg(struct iio_dev *indio_dev, unsigned int reg,
|
||
|
|
unsigned int writeval, unsigned int *readval);
|
||
|
|
|
||
|
|
int inv_icm42600_core_probe(struct regmap *regmap, int chip, int irq,
|
||
|
|
inv_icm42600_bus_setup bus_setup);
|
||
|
|
|
||
|
|
struct iio_dev *inv_icm42600_gyro_init(struct inv_icm42600_state *st);
|
||
|
|
|
||
|
|
int inv_icm42600_gyro_parse_fifo(struct iio_dev *indio_dev);
|
||
|
|
|
||
|
|
struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st);
|
||
|
|
|
||
|
|
int inv_icm42600_accel_parse_fifo(struct iio_dev *indio_dev);
|
||
|
|
|
||
|
|
#endif
|