104 lines
6.0 KiB
C
104 lines
6.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2014-2015 Cisco Systems, Inc. and/or its affiliates.
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* All rights reserved.
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*/
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#ifndef M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_H
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#define M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_H
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/*******************************************************************
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* Register Block
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* M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_VHD_REGMAP
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*******************************************************************/
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struct m00233_video_measure_regmap {
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uint32_t irq_status; /* Reg 0x0000 */
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/* The vertical counter starts on rising edge of vsync */
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uint32_t vsync_time; /* Reg 0x0004 */
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uint32_t vback_porch; /* Reg 0x0008 */
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uint32_t vactive_area; /* Reg 0x000c */
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uint32_t vfront_porch; /* Reg 0x0010 */
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/* The horizontal counter starts on rising edge of hsync. */
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uint32_t hsync_time; /* Reg 0x0014 */
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uint32_t hback_porch; /* Reg 0x0018 */
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uint32_t hactive_area; /* Reg 0x001c */
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uint32_t hfront_porch; /* Reg 0x0020 */
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uint32_t control; /* Reg 0x0024, Default=0x0 */
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uint32_t irq_triggers; /* Reg 0x0028, Default=0xff */
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/* Value is given in number of register bus clock periods between */
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/* falling and rising edge of hsync. Must be non-zero. */
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uint32_t hsync_timeout_val; /* Reg 0x002c, Default=0x1fff */
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uint32_t status; /* Reg 0x0030 */
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};
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#define M00233_VIDEO_MEASURE_REG_IRQ_STATUS_OFST 0
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#define M00233_VIDEO_MEASURE_REG_VSYNC_TIME_OFST 4
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#define M00233_VIDEO_MEASURE_REG_VBACK_PORCH_OFST 8
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#define M00233_VIDEO_MEASURE_REG_VACTIVE_AREA_OFST 12
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#define M00233_VIDEO_MEASURE_REG_VFRONT_PORCH_OFST 16
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#define M00233_VIDEO_MEASURE_REG_HSYNC_TIME_OFST 20
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#define M00233_VIDEO_MEASURE_REG_HBACK_PORCH_OFST 24
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#define M00233_VIDEO_MEASURE_REG_HACTIVE_AREA_OFST 28
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#define M00233_VIDEO_MEASURE_REG_HFRONT_PORCH_OFST 32
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#define M00233_VIDEO_MEASURE_REG_CONTROL_OFST 36
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#define M00233_VIDEO_MEASURE_REG_IRQ_TRIGGERS_OFST 40
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#define M00233_VIDEO_MEASURE_REG_HSYNC_TIMEOUT_VAL_OFST 44
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#define M00233_VIDEO_MEASURE_REG_STATUS_OFST 48
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/*******************************************************************
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* Bit Mask for register
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* M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_VHD_BITMAP
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*******************************************************************/
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/* irq_status [7:0] */
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#define M00233_IRQ_STATUS_BITMAP_VSYNC_TIME_OFST (0)
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#define M00233_IRQ_STATUS_BITMAP_VSYNC_TIME_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_VSYNC_TIME_OFST)
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#define M00233_IRQ_STATUS_BITMAP_VBACK_PORCH_OFST (1)
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#define M00233_IRQ_STATUS_BITMAP_VBACK_PORCH_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_VBACK_PORCH_OFST)
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#define M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_OFST (2)
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#define M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_OFST)
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#define M00233_IRQ_STATUS_BITMAP_VFRONT_PORCH_OFST (3)
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#define M00233_IRQ_STATUS_BITMAP_VFRONT_PORCH_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_VFRONT_PORCH_OFST)
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#define M00233_IRQ_STATUS_BITMAP_HSYNC_TIME_OFST (4)
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#define M00233_IRQ_STATUS_BITMAP_HSYNC_TIME_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_HSYNC_TIME_OFST)
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#define M00233_IRQ_STATUS_BITMAP_HBACK_PORCH_OFST (5)
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#define M00233_IRQ_STATUS_BITMAP_HBACK_PORCH_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_HBACK_PORCH_OFST)
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#define M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_OFST (6)
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#define M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_OFST)
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#define M00233_IRQ_STATUS_BITMAP_HFRONT_PORCH_OFST (7)
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#define M00233_IRQ_STATUS_BITMAP_HFRONT_PORCH_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_HFRONT_PORCH_OFST)
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/* control [4:0] */
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#define M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_OFST (0)
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#define M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_MSK (0x1 << M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_OFST)
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#define M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_OFST (1)
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#define M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_MSK (0x1 << M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_OFST)
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#define M00233_CONTROL_BITMAP_ENABLE_MEASURE_OFST (2)
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#define M00233_CONTROL_BITMAP_ENABLE_MEASURE_MSK (0x1 << M00233_CONTROL_BITMAP_ENABLE_MEASURE_OFST)
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#define M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_OFST (3)
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#define M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_MSK (0x1 << M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_OFST)
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#define M00233_CONTROL_BITMAP_UPDATE_ON_HSYNC_OFST (4)
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#define M00233_CONTROL_BITMAP_UPDATE_ON_HSYNC_MSK (0x1 << M00233_CONTROL_BITMAP_UPDATE_ON_HSYNC_OFST)
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/* irq_triggers [7:0] */
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#define M00233_IRQ_TRIGGERS_BITMAP_VSYNC_TIME_OFST (0)
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#define M00233_IRQ_TRIGGERS_BITMAP_VSYNC_TIME_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VSYNC_TIME_OFST)
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#define M00233_IRQ_TRIGGERS_BITMAP_VBACK_PORCH_OFST (1)
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#define M00233_IRQ_TRIGGERS_BITMAP_VBACK_PORCH_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VBACK_PORCH_OFST)
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#define M00233_IRQ_TRIGGERS_BITMAP_VACTIVE_AREA_OFST (2)
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#define M00233_IRQ_TRIGGERS_BITMAP_VACTIVE_AREA_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VACTIVE_AREA_OFST)
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#define M00233_IRQ_TRIGGERS_BITMAP_VFRONT_PORCH_OFST (3)
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#define M00233_IRQ_TRIGGERS_BITMAP_VFRONT_PORCH_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VFRONT_PORCH_OFST)
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#define M00233_IRQ_TRIGGERS_BITMAP_HSYNC_TIME_OFST (4)
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#define M00233_IRQ_TRIGGERS_BITMAP_HSYNC_TIME_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HSYNC_TIME_OFST)
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#define M00233_IRQ_TRIGGERS_BITMAP_HBACK_PORCH_OFST (5)
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#define M00233_IRQ_TRIGGERS_BITMAP_HBACK_PORCH_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HBACK_PORCH_OFST)
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#define M00233_IRQ_TRIGGERS_BITMAP_HACTIVE_AREA_OFST (6)
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#define M00233_IRQ_TRIGGERS_BITMAP_HACTIVE_AREA_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HACTIVE_AREA_OFST)
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#define M00233_IRQ_TRIGGERS_BITMAP_HFRONT_PORCH_OFST (7)
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#define M00233_IRQ_TRIGGERS_BITMAP_HFRONT_PORCH_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HFRONT_PORCH_OFST)
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/* status [1:0] */
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#define M00233_STATUS_BITMAP_HSYNC_TIMEOUT_OFST (0)
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#define M00233_STATUS_BITMAP_HSYNC_TIMEOUT_MSK (0x1 << M00233_STATUS_BITMAP_HSYNC_TIMEOUT_OFST)
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#define M00233_STATUS_BITMAP_INIT_DONE_OFST (1)
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#define M00233_STATUS_BITMAP_INIT_DONE_MSK (0x1 << M00233_STATUS_BITMAP_INIT_DONE_OFST)
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#endif /*M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_H*/
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