453 lines
13 KiB
C
453 lines
13 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Driver for the Conexant CX23885 PCIe bridge
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*
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* Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
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*/
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#ifndef _CX23885_REG_H_
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#define _CX23885_REG_H_
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/*
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Address Map
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0x00000000 -> 0x00009000 TX SRAM (Fifos)
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0x00010000 -> 0x00013c00 RX SRAM CMDS + CDT
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EACH CMDS struct is 0x80 bytes long
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DMAx_PTR1 = 0x03040 address of first cluster
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DMAx_PTR2 = 0x10600 address of the CDT
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DMAx_CNT1 = cluster size in (bytes >> 4) -1
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DMAx_CNT2 = total cdt size for all entries >> 3
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Cluster Descriptor entry = 4 DWORDS
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DWORD 0 -> ptr to cluster
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DWORD 1 Reserved
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DWORD 2 Reserved
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DWORD 3 Reserved
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Channel manager Data Structure entry = 20 DWORD
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0 IntialProgramCounterLow
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1 IntialProgramCounterHigh
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2 ClusterDescriptorTableBase
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3 ClusterDescriptorTableSize
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4 InstructionQueueBase
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5 InstructionQueueSize
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... Reserved
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19 Reserved
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*/
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/* Risc Instructions */
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#define RISC_CNT_INC 0x00010000
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#define RISC_CNT_RESET 0x00030000
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#define RISC_IRQ1 0x01000000
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#define RISC_IRQ2 0x02000000
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#define RISC_EOL 0x04000000
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#define RISC_SOL 0x08000000
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#define RISC_WRITE 0x10000000
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#define RISC_SKIP 0x20000000
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#define RISC_JUMP 0x70000000
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#define RISC_SYNC 0x80000000
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#define RISC_RESYNC 0x80008000
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#define RISC_READ 0x90000000
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#define RISC_WRITERM 0xB0000000
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#define RISC_WRITECM 0xC0000000
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#define RISC_WRITECR 0xD0000000
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#define RISC_WRITEC 0x50000000
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#define RISC_READC 0xA0000000
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/* Audio and Video Core */
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#define HOST_REG1 0x00000000
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#define HOST_REG2 0x00000001
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#define HOST_REG3 0x00000002
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/* Chip Configuration Registers */
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#define CHIP_CTRL 0x00000100
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#define AFE_CTRL 0x00000104
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#define VID_PLL_INT_POST 0x00000108
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#define VID_PLL_FRAC 0x0000010C
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#define AUX_PLL_INT_POST 0x00000110
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#define AUX_PLL_FRAC 0x00000114
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#define SYS_PLL_INT_POST 0x00000118
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#define SYS_PLL_FRAC 0x0000011C
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#define PIN_CTRL 0x00000120
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#define AUD_IO_CTRL 0x00000124
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#define AUD_LOCK1 0x00000128
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#define AUD_LOCK2 0x0000012C
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#define POWER_CTRL 0x00000130
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#define AFE_DIAG_CTRL1 0x00000134
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#define AFE_DIAG_CTRL3 0x0000013C
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#define PLL_DIAG_CTRL 0x00000140
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#define AFE_CLK_OUT_CTRL 0x00000144
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#define DLL1_DIAG_CTRL 0x0000015C
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/* GPIO[23:19] Output Enable */
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#define GPIO2_OUT_EN_REG 0x00000160
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/* GPIO[23:19] Data Registers */
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#define GPIO2 0x00000164
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#define IFADC_CTRL 0x00000180
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/* Infrared Remote Registers */
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#define IR_CNTRL_REG 0x00000200
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#define IR_TXCLK_REG 0x00000204
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#define IR_RXCLK_REG 0x00000208
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#define IR_CDUTY_REG 0x0000020C
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#define IR_STAT_REG 0x00000210
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#define IR_IRQEN_REG 0x00000214
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#define IR_FILTR_REG 0x00000218
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#define IR_FIFO_REG 0x0000023C
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/* Video Decoder Registers */
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#define MODE_CTRL 0x00000400
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#define OUT_CTRL1 0x00000404
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#define OUT_CTRL2 0x00000408
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#define GEN_STAT 0x0000040C
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#define INT_STAT_MASK 0x00000410
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#define LUMA_CTRL 0x00000414
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#define HSCALE_CTRL 0x00000418
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#define VSCALE_CTRL 0x0000041C
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#define CHROMA_CTRL 0x00000420
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#define VBI_LINE_CTRL1 0x00000424
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#define VBI_LINE_CTRL2 0x00000428
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#define VBI_LINE_CTRL3 0x0000042C
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#define VBI_LINE_CTRL4 0x00000430
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#define VBI_LINE_CTRL5 0x00000434
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#define VBI_FC_CFG 0x00000438
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#define VBI_MISC_CFG1 0x0000043C
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#define VBI_MISC_CFG2 0x00000440
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#define VBI_PAY1 0x00000444
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#define VBI_PAY2 0x00000448
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#define VBI_CUST1_CFG1 0x0000044C
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#define VBI_CUST1_CFG2 0x00000450
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#define VBI_CUST1_CFG3 0x00000454
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#define VBI_CUST2_CFG1 0x00000458
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#define VBI_CUST2_CFG2 0x0000045C
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#define VBI_CUST2_CFG3 0x00000460
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#define VBI_CUST3_CFG1 0x00000464
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#define VBI_CUST3_CFG2 0x00000468
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#define VBI_CUST3_CFG3 0x0000046C
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#define HORIZ_TIM_CTRL 0x00000470
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#define VERT_TIM_CTRL 0x00000474
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#define SRC_COMB_CFG 0x00000478
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#define CHROMA_VBIOFF_CFG 0x0000047C
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#define FIELD_COUNT 0x00000480
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#define MISC_TIM_CTRL 0x00000484
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#define DFE_CTRL1 0x00000488
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#define DFE_CTRL2 0x0000048C
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#define DFE_CTRL3 0x00000490
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#define PLL_CTRL 0x00000494
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#define HTL_CTRL 0x00000498
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#define COMB_CTRL 0x0000049C
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#define CRUSH_CTRL 0x000004A0
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#define SOFT_RST_CTRL 0x000004A4
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#define CX885_VERSION 0x000004B4
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#define VBI_PASS_CTRL 0x000004BC
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/* Audio Decoder Registers */
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/* 8051 Configuration */
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#define DL_CTL 0x00000800
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#define STD_DET_STATUS 0x00000804
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#define STD_DET_CTL 0x00000808
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#define DW8051_INT 0x0000080C
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#define GENERAL_CTL 0x00000810
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#define AAGC_CTL 0x00000814
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#define DEMATRIX_CTL 0x000008CC
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#define PATH1_CTL1 0x000008D0
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#define PATH1_VOL_CTL 0x000008D4
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#define PATH1_EQ_CTL 0x000008D8
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#define PATH1_SC_CTL 0x000008DC
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#define PATH2_CTL1 0x000008E0
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#define PATH2_VOL_CTL 0x000008E4
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#define PATH2_EQ_CTL 0x000008E8
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#define PATH2_SC_CTL 0x000008EC
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/* Sample Rate Converter */
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#define SRC_CTL 0x000008F0
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#define SRC_LF_COEF 0x000008F4
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#define SRC1_CTL 0x000008F8
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#define SRC2_CTL 0x000008FC
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#define SRC3_CTL 0x00000900
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#define SRC4_CTL 0x00000904
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#define SRC5_CTL 0x00000908
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#define SRC6_CTL 0x0000090C
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#define BAND_OUT_SEL 0x00000910
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#define I2S_N_CTL 0x00000914
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#define I2S_OUT_CTL 0x00000918
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#define AUTOCONFIG_REG 0x000009C4
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/* Audio ADC Registers */
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#define DSM_CTRL1 0x00000000
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#define DSM_CTRL2 0x00000001
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#define CHP_EN_CTRL 0x00000002
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#define CHP_CLK_CTRL1 0x00000004
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#define CHP_CLK_CTRL2 0x00000005
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#define BG_REF_CTRL 0x00000006
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#define SD2_SW_CTRL1 0x00000008
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#define SD2_SW_CTRL2 0x00000009
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#define SD2_BIAS_CTRL 0x0000000A
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#define AMP_BIAS_CTRL 0x0000000C
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#define CH_PWR_CTRL1 0x0000000E
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#define FLD_CH_SEL (1 << 3)
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#define CH_PWR_CTRL2 0x0000000F
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#define DSM_STATUS1 0x00000010
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#define DSM_STATUS2 0x00000011
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#define DIG_CTL1 0x00000012
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#define DIG_CTL2 0x00000013
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#define I2S_TX_CFG 0x0000001A
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#define DEV_CNTRL2 0x00040000
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#define PCI_MSK_IR (1 << 28)
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#define PCI_MSK_AV_CORE (1 << 27)
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#define PCI_MSK_GPIO1 (1 << 24)
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#define PCI_MSK_GPIO0 (1 << 23)
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#define PCI_MSK_APB_DMA (1 << 12)
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#define PCI_MSK_AL_WR (1 << 11)
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#define PCI_MSK_AL_RD (1 << 10)
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#define PCI_MSK_RISC_WR (1 << 9)
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#define PCI_MSK_RISC_RD (1 << 8)
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#define PCI_MSK_AUD_EXT (1 << 4)
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#define PCI_MSK_AUD_INT (1 << 3)
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#define PCI_MSK_VID_C (1 << 2)
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#define PCI_MSK_VID_B (1 << 1)
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#define PCI_MSK_VID_A 1
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#define PCI_INT_MSK 0x00040010
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#define PCI_INT_STAT 0x00040014
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#define PCI_INT_MSTAT 0x00040018
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#define VID_A_INT_MSK 0x00040020
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#define VID_A_INT_STAT 0x00040024
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#define VID_A_INT_MSTAT 0x00040028
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#define VID_A_INT_SSTAT 0x0004002C
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#define VID_B_INT_MSK 0x00040030
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#define VID_B_MSK_BAD_PKT (1 << 20)
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#define VID_B_MSK_VBI_OPC_ERR (1 << 17)
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#define VID_B_MSK_OPC_ERR (1 << 16)
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#define VID_B_MSK_VBI_SYNC (1 << 13)
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#define VID_B_MSK_SYNC (1 << 12)
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#define VID_B_MSK_VBI_OF (1 << 9)
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#define VID_B_MSK_OF (1 << 8)
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#define VID_B_MSK_VBI_RISCI2 (1 << 5)
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#define VID_B_MSK_RISCI2 (1 << 4)
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#define VID_B_MSK_VBI_RISCI1 (1 << 1)
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#define VID_B_MSK_RISCI1 1
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#define VID_B_INT_STAT 0x00040034
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#define VID_B_INT_MSTAT 0x00040038
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#define VID_B_INT_SSTAT 0x0004003C
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#define VID_B_MSK_BAD_PKT (1 << 20)
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#define VID_B_MSK_OPC_ERR (1 << 16)
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#define VID_B_MSK_SYNC (1 << 12)
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#define VID_B_MSK_OF (1 << 8)
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#define VID_B_MSK_RISCI2 (1 << 4)
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#define VID_B_MSK_RISCI1 1
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#define VID_C_MSK_BAD_PKT (1 << 20)
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#define VID_C_MSK_OPC_ERR (1 << 16)
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#define VID_C_MSK_SYNC (1 << 12)
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#define VID_C_MSK_OF (1 << 8)
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#define VID_C_MSK_RISCI2 (1 << 4)
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#define VID_C_MSK_RISCI1 1
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/* A superset for testing purposes */
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#define VID_BC_MSK_BAD_PKT (1 << 20)
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#define VID_BC_MSK_OPC_ERR (1 << 16)
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#define VID_BC_MSK_SYNC (1 << 12)
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#define VID_BC_MSK_OF (1 << 8)
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#define VID_BC_MSK_VBI_RISCI2 (1 << 5)
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#define VID_BC_MSK_RISCI2 (1 << 4)
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#define VID_BC_MSK_VBI_RISCI1 (1 << 1)
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#define VID_BC_MSK_RISCI1 1
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#define VID_C_INT_MSK 0x00040040
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#define VID_C_INT_STAT 0x00040044
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#define VID_C_INT_MSTAT 0x00040048
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#define VID_C_INT_SSTAT 0x0004004C
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#define AUDIO_INT_INT_MSK 0x00040050
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#define AUDIO_INT_INT_STAT 0x00040054
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#define AUDIO_INT_INT_MSTAT 0x00040058
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#define AUDIO_INT_INT_SSTAT 0x0004005C
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#define AUDIO_EXT_INT_MSK 0x00040060
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#define AUDIO_EXT_INT_STAT 0x00040064
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#define AUDIO_EXT_INT_MSTAT 0x00040068
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#define AUDIO_EXT_INT_SSTAT 0x0004006C
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/* Bits [7:0] set in both TC_REQ and TC_REQ_SET
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* indicate a stall in the RISC engine for a
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* particular rider traffic class. This causes
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* the 885 and 888 bridges (unknown about 887)
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* to become inoperable. Setting bits in
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* TC_REQ_SET resets the corresponding bits
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* in TC_REQ (and TC_REQ_SET) allowing
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* operation to continue.
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*/
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#define TC_REQ 0x00040090
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#define TC_REQ_SET 0x00040094
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#define RDR_CFG0 0x00050000
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#define RDR_CFG1 0x00050004
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#define RDR_CFG2 0x00050008
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#define RDR_RDRCTL1 0x0005030c
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#define RDR_TLCTL0 0x00050318
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/* APB DMAC Current Buffer Pointer */
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#define DMA1_PTR1 0x00100000
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#define DMA2_PTR1 0x00100004
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#define DMA3_PTR1 0x00100008
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#define DMA4_PTR1 0x0010000C
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#define DMA5_PTR1 0x00100010
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#define DMA6_PTR1 0x00100014
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#define DMA7_PTR1 0x00100018
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#define DMA8_PTR1 0x0010001C
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/* APB DMAC Current Table Pointer */
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#define DMA1_PTR2 0x00100040
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#define DMA2_PTR2 0x00100044
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#define DMA3_PTR2 0x00100048
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#define DMA4_PTR2 0x0010004C
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#define DMA5_PTR2 0x00100050
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#define DMA6_PTR2 0x00100054
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#define DMA7_PTR2 0x00100058
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#define DMA8_PTR2 0x0010005C
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/* APB DMAC Buffer Limit */
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#define DMA1_CNT1 0x00100080
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#define DMA2_CNT1 0x00100084
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#define DMA3_CNT1 0x00100088
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#define DMA4_CNT1 0x0010008C
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#define DMA5_CNT1 0x00100090
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#define DMA6_CNT1 0x00100094
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#define DMA7_CNT1 0x00100098
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#define DMA8_CNT1 0x0010009C
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||
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|
||
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/* APB DMAC Table Size */
|
||
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#define DMA1_CNT2 0x001000C0
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||
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#define DMA2_CNT2 0x001000C4
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||
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#define DMA3_CNT2 0x001000C8
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||
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#define DMA4_CNT2 0x001000CC
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||
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#define DMA5_CNT2 0x001000D0
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||
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#define DMA6_CNT2 0x001000D4
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||
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#define DMA7_CNT2 0x001000D8
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||
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#define DMA8_CNT2 0x001000DC
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||
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|
|
||
|
|
/* Timer Counters */
|
||
|
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#define TM_CNT_LDW 0x00110000
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||
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#define TM_CNT_UW 0x00110004
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||
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#define TM_LMT_LDW 0x00110008
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||
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|
#define TM_LMT_UW 0x0011000C
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||
|
|
|
||
|
|
/* GPIO */
|
||
|
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#define GP0_IO 0x00110010
|
||
|
|
#define GPIO_ISM 0x00110014
|
||
|
|
#define SOFT_RESET 0x0011001C
|
||
|
|
|
||
|
|
/* GPIO (417 Microsoftcontroller) RW Data */
|
||
|
|
#define MC417_RWD 0x00110020
|
||
|
|
|
||
|
|
/* GPIO (417 Microsoftcontroller) Output Enable, Low Active */
|
||
|
|
#define MC417_OEN 0x00110024
|
||
|
|
#define MC417_CTL 0x00110028
|
||
|
|
#define ALT_PIN_OUT_SEL 0x0011002C
|
||
|
|
#define CLK_DELAY 0x00110048
|
||
|
|
#define PAD_CTRL 0x0011004C
|
||
|
|
|
||
|
|
/* Video A Interface */
|
||
|
|
#define VID_A_GPCNT 0x00130020
|
||
|
|
#define VBI_A_GPCNT 0x00130024
|
||
|
|
#define VID_A_GPCNT_CTL 0x00130030
|
||
|
|
#define VBI_A_GPCNT_CTL 0x00130034
|
||
|
|
#define VID_A_DMA_CTL 0x00130040
|
||
|
|
#define VID_A_VIP_CTRL 0x00130080
|
||
|
|
#define VID_A_PIXEL_FRMT 0x00130084
|
||
|
|
#define VID_A_VBI_CTRL 0x00130088
|
||
|
|
|
||
|
|
/* Video B Interface */
|
||
|
|
#define VID_B_DMA 0x00130100
|
||
|
|
#define VBI_B_DMA 0x00130108
|
||
|
|
#define VID_B_GPCNT 0x00130120
|
||
|
|
#define VBI_B_GPCNT 0x00130124
|
||
|
|
#define VID_B_GPCNT_CTL 0x00130134
|
||
|
|
#define VBI_B_GPCNT_CTL 0x00130138
|
||
|
|
#define VID_B_DMA_CTL 0x00130140
|
||
|
|
#define VID_B_SRC_SEL 0x00130144
|
||
|
|
#define VID_B_LNGTH 0x00130150
|
||
|
|
#define VID_B_HW_SOP_CTL 0x00130154
|
||
|
|
#define VID_B_GEN_CTL 0x00130158
|
||
|
|
#define VID_B_BD_PKT_STATUS 0x0013015C
|
||
|
|
#define VID_B_SOP_STATUS 0x00130160
|
||
|
|
#define VID_B_FIFO_OVFL_STAT 0x00130164
|
||
|
|
#define VID_B_VLD_MISC 0x00130168
|
||
|
|
#define VID_B_TS_CLK_EN 0x0013016C
|
||
|
|
#define VID_B_VIP_CTRL 0x00130180
|
||
|
|
#define VID_B_PIXEL_FRMT 0x00130184
|
||
|
|
|
||
|
|
/* Video C Interface */
|
||
|
|
#define VID_C_DMA 0x00130200
|
||
|
|
#define VBI_C_DMA 0x00130208
|
||
|
|
#define VID_C_GPCNT 0x00130220
|
||
|
|
#define VID_C_GPCNT_CTL 0x00130230
|
||
|
|
#define VBI_C_GPCNT_CTL 0x00130234
|
||
|
|
#define VID_C_DMA_CTL 0x00130240
|
||
|
|
#define VID_C_LNGTH 0x00130250
|
||
|
|
#define VID_C_HW_SOP_CTL 0x00130254
|
||
|
|
#define VID_C_GEN_CTL 0x00130258
|
||
|
|
#define VID_C_BD_PKT_STATUS 0x0013025C
|
||
|
|
#define VID_C_SOP_STATUS 0x00130260
|
||
|
|
#define VID_C_FIFO_OVFL_STAT 0x00130264
|
||
|
|
#define VID_C_VLD_MISC 0x00130268
|
||
|
|
#define VID_C_TS_CLK_EN 0x0013026C
|
||
|
|
|
||
|
|
/* Internal Audio Interface */
|
||
|
|
#define AUD_INT_A_GPCNT 0x00140020
|
||
|
|
#define AUD_INT_B_GPCNT 0x00140024
|
||
|
|
#define AUD_INT_A_GPCNT_CTL 0x00140030
|
||
|
|
#define AUD_INT_B_GPCNT_CTL 0x00140034
|
||
|
|
#define AUD_INT_DMA_CTL 0x00140040
|
||
|
|
#define AUD_INT_A_LNGTH 0x00140050
|
||
|
|
#define AUD_INT_B_LNGTH 0x00140054
|
||
|
|
#define AUD_INT_A_MODE 0x00140058
|
||
|
|
#define AUD_INT_B_MODE 0x0014005C
|
||
|
|
|
||
|
|
/* External Audio Interface */
|
||
|
|
#define AUD_EXT_DMA 0x00140100
|
||
|
|
#define AUD_EXT_GPCNT 0x00140120
|
||
|
|
#define AUD_EXT_GPCNT_CTL 0x00140130
|
||
|
|
#define AUD_EXT_DMA_CTL 0x00140140
|
||
|
|
#define AUD_EXT_LNGTH 0x00140150
|
||
|
|
#define AUD_EXT_A_MODE 0x00140158
|
||
|
|
|
||
|
|
/* I2C Bus 1 */
|
||
|
|
#define I2C1_ADDR 0x00180000
|
||
|
|
#define I2C1_WDATA 0x00180004
|
||
|
|
#define I2C1_CTRL 0x00180008
|
||
|
|
#define I2C1_RDATA 0x0018000C
|
||
|
|
#define I2C1_STAT 0x00180010
|
||
|
|
|
||
|
|
/* I2C Bus 2 */
|
||
|
|
#define I2C2_ADDR 0x00190000
|
||
|
|
#define I2C2_WDATA 0x00190004
|
||
|
|
#define I2C2_CTRL 0x00190008
|
||
|
|
#define I2C2_RDATA 0x0019000C
|
||
|
|
#define I2C2_STAT 0x00190010
|
||
|
|
|
||
|
|
/* I2C Bus 3 */
|
||
|
|
#define I2C3_ADDR 0x001A0000
|
||
|
|
#define I2C3_WDATA 0x001A0004
|
||
|
|
#define I2C3_CTRL 0x001A0008
|
||
|
|
#define I2C3_RDATA 0x001A000C
|
||
|
|
#define I2C3_STAT 0x001A0010
|
||
|
|
|
||
|
|
/* UART */
|
||
|
|
#define UART_CTL 0x001B0000
|
||
|
|
#define UART_BRD 0x001B0004
|
||
|
|
#define UART_ISR 0x001B000C
|
||
|
|
#define UART_CNT 0x001B0010
|
||
|
|
|
||
|
|
#endif /* _CX23885_REG_H_ */
|