552 lines
13 KiB
C
552 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* NVIDIA Tegra Video decoder driver
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*
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* Copyright (C) 2016-2017 Dmitry Osipenko <digetx@gmail.com>
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*
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*/
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#include <linux/clk.h>
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#include <linux/dma-buf.h>
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#include <linux/genalloc.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/uaccess.h>
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#include <soc/tegra/common.h>
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#include <soc/tegra/pmc.h>
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#include "vde.h"
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#define CREATE_TRACE_POINTS
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#include "trace.h"
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void tegra_vde_writel(struct tegra_vde *vde, u32 value,
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void __iomem *base, u32 offset)
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{
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trace_vde_writel(vde, base, offset, value);
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writel_relaxed(value, base + offset);
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}
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u32 tegra_vde_readl(struct tegra_vde *vde, void __iomem *base, u32 offset)
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{
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u32 value = readl_relaxed(base + offset);
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trace_vde_readl(vde, base, offset, value);
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return value;
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}
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void tegra_vde_set_bits(struct tegra_vde *vde, u32 mask,
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void __iomem *base, u32 offset)
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{
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u32 value = tegra_vde_readl(vde, base, offset);
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tegra_vde_writel(vde, value | mask, base, offset);
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}
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int tegra_vde_alloc_bo(struct tegra_vde *vde,
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struct tegra_vde_bo **ret_bo,
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enum dma_data_direction dma_dir,
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size_t size)
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{
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struct device *dev = vde->dev;
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struct tegra_vde_bo *bo;
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int err;
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bo = kzalloc(sizeof(*bo), GFP_KERNEL);
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if (!bo)
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return -ENOMEM;
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bo->vde = vde;
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bo->size = size;
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bo->dma_dir = dma_dir;
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bo->dma_attrs = DMA_ATTR_WRITE_COMBINE |
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DMA_ATTR_NO_KERNEL_MAPPING;
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if (!vde->domain)
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bo->dma_attrs |= DMA_ATTR_FORCE_CONTIGUOUS;
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bo->dma_cookie = dma_alloc_attrs(dev, bo->size, &bo->dma_handle,
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GFP_KERNEL, bo->dma_attrs);
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if (!bo->dma_cookie) {
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dev_err(dev, "Failed to allocate DMA buffer of size: %zu\n",
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bo->size);
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err = -ENOMEM;
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goto free_bo;
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}
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err = dma_get_sgtable_attrs(dev, &bo->sgt, bo->dma_cookie,
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bo->dma_handle, bo->size, bo->dma_attrs);
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if (err) {
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dev_err(dev, "Failed to get DMA buffer SG table: %d\n", err);
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goto free_attrs;
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}
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err = dma_map_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs);
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if (err) {
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dev_err(dev, "Failed to map DMA buffer SG table: %d\n", err);
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goto free_table;
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}
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if (vde->domain) {
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err = tegra_vde_iommu_map(vde, &bo->sgt, &bo->iova, bo->size);
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if (err) {
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dev_err(dev, "Failed to map DMA buffer IOVA: %d\n", err);
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goto unmap_sgtable;
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}
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bo->dma_addr = iova_dma_addr(&vde->iova, bo->iova);
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} else {
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bo->dma_addr = sg_dma_address(bo->sgt.sgl);
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}
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*ret_bo = bo;
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return 0;
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unmap_sgtable:
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dma_unmap_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs);
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free_table:
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sg_free_table(&bo->sgt);
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free_attrs:
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dma_free_attrs(dev, bo->size, bo->dma_cookie, bo->dma_handle,
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bo->dma_attrs);
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free_bo:
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kfree(bo);
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return err;
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}
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void tegra_vde_free_bo(struct tegra_vde_bo *bo)
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{
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struct tegra_vde *vde = bo->vde;
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struct device *dev = vde->dev;
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if (vde->domain)
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tegra_vde_iommu_unmap(vde, bo->iova);
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dma_unmap_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs);
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sg_free_table(&bo->sgt);
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dma_free_attrs(dev, bo->size, bo->dma_cookie, bo->dma_handle,
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bo->dma_attrs);
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kfree(bo);
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}
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static irqreturn_t tegra_vde_isr(int irq, void *data)
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{
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struct tegra_vde *vde = data;
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if (completion_done(&vde->decode_completion))
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return IRQ_NONE;
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tegra_vde_set_bits(vde, 0, vde->frameid, 0x208);
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complete(&vde->decode_completion);
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return IRQ_HANDLED;
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}
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static __maybe_unused int tegra_vde_runtime_suspend(struct device *dev)
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{
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struct tegra_vde *vde = dev_get_drvdata(dev);
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int err;
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if (!dev->pm_domain) {
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err = tegra_powergate_power_off(TEGRA_POWERGATE_VDEC);
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if (err) {
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dev_err(dev, "Failed to power down HW: %d\n", err);
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return err;
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}
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}
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clk_disable_unprepare(vde->clk);
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reset_control_release(vde->rst);
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reset_control_release(vde->rst_mc);
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return 0;
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}
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static __maybe_unused int tegra_vde_runtime_resume(struct device *dev)
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{
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struct tegra_vde *vde = dev_get_drvdata(dev);
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int err;
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err = reset_control_acquire(vde->rst_mc);
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if (err) {
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dev_err(dev, "Failed to acquire mc reset: %d\n", err);
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return err;
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}
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err = reset_control_acquire(vde->rst);
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if (err) {
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dev_err(dev, "Failed to acquire reset: %d\n", err);
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goto release_mc_reset;
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}
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if (!dev->pm_domain) {
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err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_VDEC,
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vde->clk, vde->rst);
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if (err) {
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dev_err(dev, "Failed to power up HW : %d\n", err);
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goto release_reset;
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}
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} else {
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/*
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* tegra_powergate_sequence_power_up() leaves clocks enabled,
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* while GENPD not.
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*/
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err = clk_prepare_enable(vde->clk);
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if (err) {
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dev_err(dev, "Failed to enable clock: %d\n", err);
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goto release_reset;
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}
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}
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return 0;
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release_reset:
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reset_control_release(vde->rst);
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release_mc_reset:
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reset_control_release(vde->rst_mc);
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return err;
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}
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static int tegra_vde_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct tegra_vde *vde;
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int irq, err;
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vde = devm_kzalloc(dev, sizeof(*vde), GFP_KERNEL);
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if (!vde)
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return -ENOMEM;
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platform_set_drvdata(pdev, vde);
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vde->soc = of_device_get_match_data(&pdev->dev);
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vde->dev = dev;
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vde->sxe = devm_platform_ioremap_resource_byname(pdev, "sxe");
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if (IS_ERR(vde->sxe))
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return PTR_ERR(vde->sxe);
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vde->bsev = devm_platform_ioremap_resource_byname(pdev, "bsev");
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if (IS_ERR(vde->bsev))
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return PTR_ERR(vde->bsev);
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vde->mbe = devm_platform_ioremap_resource_byname(pdev, "mbe");
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if (IS_ERR(vde->mbe))
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return PTR_ERR(vde->mbe);
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vde->ppe = devm_platform_ioremap_resource_byname(pdev, "ppe");
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if (IS_ERR(vde->ppe))
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return PTR_ERR(vde->ppe);
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vde->mce = devm_platform_ioremap_resource_byname(pdev, "mce");
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if (IS_ERR(vde->mce))
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return PTR_ERR(vde->mce);
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vde->tfe = devm_platform_ioremap_resource_byname(pdev, "tfe");
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if (IS_ERR(vde->tfe))
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return PTR_ERR(vde->tfe);
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vde->ppb = devm_platform_ioremap_resource_byname(pdev, "ppb");
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if (IS_ERR(vde->ppb))
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return PTR_ERR(vde->ppb);
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vde->vdma = devm_platform_ioremap_resource_byname(pdev, "vdma");
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if (IS_ERR(vde->vdma))
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return PTR_ERR(vde->vdma);
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vde->frameid = devm_platform_ioremap_resource_byname(pdev, "frameid");
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if (IS_ERR(vde->frameid))
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return PTR_ERR(vde->frameid);
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vde->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(vde->clk)) {
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err = PTR_ERR(vde->clk);
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dev_err(dev, "Could not get VDE clk %d\n", err);
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return err;
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}
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vde->rst = devm_reset_control_get_exclusive_released(dev, NULL);
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if (IS_ERR(vde->rst)) {
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err = PTR_ERR(vde->rst);
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dev_err(dev, "Could not get VDE reset %d\n", err);
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return err;
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}
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vde->rst_mc = devm_reset_control_get_optional_exclusive_released(dev, "mc");
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if (IS_ERR(vde->rst_mc)) {
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err = PTR_ERR(vde->rst_mc);
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dev_err(dev, "Could not get MC reset %d\n", err);
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return err;
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}
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irq = platform_get_irq_byname(pdev, "sync-token");
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if (irq < 0)
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return irq;
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err = devm_request_irq(dev, irq, tegra_vde_isr, 0,
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dev_name(dev), vde);
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if (err) {
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dev_err(dev, "Could not request IRQ %d\n", err);
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return err;
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}
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err = devm_tegra_core_dev_init_opp_table_common(dev);
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if (err) {
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dev_err(dev, "Could initialize OPP table %d\n", err);
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return err;
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}
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vde->iram_pool = of_gen_pool_get(dev->of_node, "iram", 0);
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if (!vde->iram_pool) {
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dev_err(dev, "Could not get IRAM pool\n");
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return -EPROBE_DEFER;
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}
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vde->iram = gen_pool_dma_alloc(vde->iram_pool,
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gen_pool_size(vde->iram_pool),
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&vde->iram_lists_addr);
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if (!vde->iram) {
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dev_err(dev, "Could not reserve IRAM\n");
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return -ENOMEM;
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}
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INIT_LIST_HEAD(&vde->map_list);
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mutex_init(&vde->map_lock);
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mutex_init(&vde->lock);
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init_completion(&vde->decode_completion);
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err = tegra_vde_iommu_init(vde);
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if (err) {
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dev_err(dev, "Failed to initialize IOMMU: %d\n", err);
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goto err_gen_free;
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}
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pm_runtime_enable(dev);
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pm_runtime_use_autosuspend(dev);
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pm_runtime_set_autosuspend_delay(dev, 300);
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/*
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* VDE partition may be left ON after bootloader, hence let's
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* power-cycle it in order to put hardware into a predictable lower
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* power state.
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*/
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err = pm_runtime_resume_and_get(dev);
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if (err)
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goto err_pm_runtime;
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pm_runtime_put(dev);
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err = tegra_vde_alloc_bo(vde, &vde->secure_bo, DMA_FROM_DEVICE, 4096);
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if (err) {
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dev_err(dev, "Failed to allocate secure BO: %d\n", err);
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goto err_pm_runtime;
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}
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err = tegra_vde_v4l2_init(vde);
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if (err) {
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dev_err(dev, "Failed to initialize V4L2: %d\n", err);
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goto err_free_secure_bo;
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}
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return 0;
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err_free_secure_bo:
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|
|
tegra_vde_free_bo(vde->secure_bo);
|
||
|
|
err_pm_runtime:
|
||
|
|
pm_runtime_dont_use_autosuspend(dev);
|
||
|
|
pm_runtime_disable(dev);
|
||
|
|
|
||
|
|
tegra_vde_iommu_deinit(vde);
|
||
|
|
|
||
|
|
err_gen_free:
|
||
|
|
gen_pool_free(vde->iram_pool, (unsigned long)vde->iram,
|
||
|
|
gen_pool_size(vde->iram_pool));
|
||
|
|
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int tegra_vde_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct tegra_vde *vde = platform_get_drvdata(pdev);
|
||
|
|
struct device *dev = &pdev->dev;
|
||
|
|
|
||
|
|
tegra_vde_v4l2_deinit(vde);
|
||
|
|
tegra_vde_free_bo(vde->secure_bo);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* As it increments RPM usage_count even on errors, we don't need to
|
||
|
|
* check the returned code here.
|
||
|
|
*/
|
||
|
|
pm_runtime_get_sync(dev);
|
||
|
|
|
||
|
|
pm_runtime_dont_use_autosuspend(dev);
|
||
|
|
pm_runtime_disable(dev);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Balance RPM state, the VDE power domain is left ON and hardware
|
||
|
|
* is clock-gated. It's safe to reboot machine now.
|
||
|
|
*/
|
||
|
|
pm_runtime_put_noidle(dev);
|
||
|
|
clk_disable_unprepare(vde->clk);
|
||
|
|
|
||
|
|
tegra_vde_dmabuf_cache_unmap_all(vde);
|
||
|
|
tegra_vde_iommu_deinit(vde);
|
||
|
|
|
||
|
|
gen_pool_free(vde->iram_pool, (unsigned long)vde->iram,
|
||
|
|
gen_pool_size(vde->iram_pool));
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void tegra_vde_shutdown(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* On some devices bootloader isn't ready to a power-gated VDE on
|
||
|
|
* a warm-reboot, machine will hang in that case.
|
||
|
|
*/
|
||
|
|
pm_runtime_get_sync(&pdev->dev);
|
||
|
|
}
|
||
|
|
|
||
|
|
static __maybe_unused int tegra_vde_pm_suspend(struct device *dev)
|
||
|
|
{
|
||
|
|
struct tegra_vde *vde = dev_get_drvdata(dev);
|
||
|
|
int err;
|
||
|
|
|
||
|
|
mutex_lock(&vde->lock);
|
||
|
|
|
||
|
|
err = pm_runtime_force_suspend(dev);
|
||
|
|
if (err < 0)
|
||
|
|
return err;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static __maybe_unused int tegra_vde_pm_resume(struct device *dev)
|
||
|
|
{
|
||
|
|
struct tegra_vde *vde = dev_get_drvdata(dev);
|
||
|
|
int err;
|
||
|
|
|
||
|
|
err = pm_runtime_force_resume(dev);
|
||
|
|
if (err < 0)
|
||
|
|
return err;
|
||
|
|
|
||
|
|
mutex_unlock(&vde->lock);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct dev_pm_ops tegra_vde_pm_ops = {
|
||
|
|
SET_RUNTIME_PM_OPS(tegra_vde_runtime_suspend,
|
||
|
|
tegra_vde_runtime_resume,
|
||
|
|
NULL)
|
||
|
|
SET_SYSTEM_SLEEP_PM_OPS(tegra_vde_pm_suspend,
|
||
|
|
tegra_vde_pm_resume)
|
||
|
|
};
|
||
|
|
|
||
|
|
static const u32 tegra124_decoded_fmts[] = {
|
||
|
|
/* TBD: T124 supports only a non-standard Tegra tiled format */
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct tegra_coded_fmt_desc tegra124_coded_fmts[] = {
|
||
|
|
{
|
||
|
|
.fourcc = V4L2_PIX_FMT_H264_SLICE,
|
||
|
|
.frmsize = {
|
||
|
|
.min_width = 16,
|
||
|
|
.max_width = 1920,
|
||
|
|
.step_width = 16,
|
||
|
|
.min_height = 16,
|
||
|
|
.max_height = 2032,
|
||
|
|
.step_height = 16,
|
||
|
|
},
|
||
|
|
.num_decoded_fmts = ARRAY_SIZE(tegra124_decoded_fmts),
|
||
|
|
.decoded_fmts = tegra124_decoded_fmts,
|
||
|
|
.decode_run = tegra_vde_h264_decode_run,
|
||
|
|
.decode_wait = tegra_vde_h264_decode_wait,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const u32 tegra20_decoded_fmts[] = {
|
||
|
|
V4L2_PIX_FMT_YUV420M,
|
||
|
|
V4L2_PIX_FMT_YVU420M,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct tegra_coded_fmt_desc tegra20_coded_fmts[] = {
|
||
|
|
{
|
||
|
|
.fourcc = V4L2_PIX_FMT_H264_SLICE,
|
||
|
|
.frmsize = {
|
||
|
|
.min_width = 16,
|
||
|
|
.max_width = 1920,
|
||
|
|
.step_width = 16,
|
||
|
|
.min_height = 16,
|
||
|
|
.max_height = 2032,
|
||
|
|
.step_height = 16,
|
||
|
|
},
|
||
|
|
.num_decoded_fmts = ARRAY_SIZE(tegra20_decoded_fmts),
|
||
|
|
.decoded_fmts = tegra20_decoded_fmts,
|
||
|
|
.decode_run = tegra_vde_h264_decode_run,
|
||
|
|
.decode_wait = tegra_vde_h264_decode_wait,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct tegra_vde_soc tegra124_vde_soc = {
|
||
|
|
.supports_ref_pic_marking = true,
|
||
|
|
.coded_fmts = tegra124_coded_fmts,
|
||
|
|
.num_coded_fmts = ARRAY_SIZE(tegra124_coded_fmts),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct tegra_vde_soc tegra114_vde_soc = {
|
||
|
|
.supports_ref_pic_marking = true,
|
||
|
|
.coded_fmts = tegra20_coded_fmts,
|
||
|
|
.num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct tegra_vde_soc tegra30_vde_soc = {
|
||
|
|
.supports_ref_pic_marking = false,
|
||
|
|
.coded_fmts = tegra20_coded_fmts,
|
||
|
|
.num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct tegra_vde_soc tegra20_vde_soc = {
|
||
|
|
.supports_ref_pic_marking = false,
|
||
|
|
.coded_fmts = tegra20_coded_fmts,
|
||
|
|
.num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id tegra_vde_of_match[] = {
|
||
|
|
{ .compatible = "nvidia,tegra124-vde", .data = &tegra124_vde_soc },
|
||
|
|
{ .compatible = "nvidia,tegra114-vde", .data = &tegra114_vde_soc },
|
||
|
|
{ .compatible = "nvidia,tegra30-vde", .data = &tegra30_vde_soc },
|
||
|
|
{ .compatible = "nvidia,tegra20-vde", .data = &tegra20_vde_soc },
|
||
|
|
{ },
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, tegra_vde_of_match);
|
||
|
|
|
||
|
|
static struct platform_driver tegra_vde_driver = {
|
||
|
|
.probe = tegra_vde_probe,
|
||
|
|
.remove = tegra_vde_remove,
|
||
|
|
.shutdown = tegra_vde_shutdown,
|
||
|
|
.driver = {
|
||
|
|
.name = "tegra-vde",
|
||
|
|
.of_match_table = tegra_vde_of_match,
|
||
|
|
.pm = &tegra_vde_pm_ops,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
module_platform_driver(tegra_vde_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("NVIDIA Tegra Video Decoder driver");
|
||
|
|
MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
|
||
|
|
MODULE_LICENSE("GPL");
|