417 lines
11 KiB
C
417 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
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* Author: Jacob Chen <jacob-chen@iotwrt.com>
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*/
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#include <linux/pm_runtime.h>
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#include "rga-hw.h"
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#include "rga.h"
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enum e_rga_start_pos {
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LT = 0,
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LB = 1,
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RT = 2,
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RB = 3,
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};
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struct rga_addr_offset {
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unsigned int y_off;
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unsigned int u_off;
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unsigned int v_off;
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};
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struct rga_corners_addr_offset {
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struct rga_addr_offset left_top;
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struct rga_addr_offset right_top;
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struct rga_addr_offset left_bottom;
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struct rga_addr_offset right_bottom;
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};
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static unsigned int rga_get_scaling(unsigned int src, unsigned int dst)
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{
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/*
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* The rga hw scaling factor is a normalized inverse of the
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* scaling factor.
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* For example: When source width is 100 and destination width is 200
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* (scaling of 2x), then the hw factor is NC * 100 / 200.
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* The normalization factor (NC) is 2^16 = 0x10000.
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*/
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return (src > dst) ? ((dst << 16) / src) : ((src << 16) / dst);
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}
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static struct rga_corners_addr_offset
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rga_get_addr_offset(struct rga_frame *frm, unsigned int x, unsigned int y,
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unsigned int w, unsigned int h)
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{
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struct rga_corners_addr_offset offsets;
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struct rga_addr_offset *lt, *lb, *rt, *rb;
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unsigned int x_div = 0,
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y_div = 0, uv_stride = 0, pixel_width = 0, uv_factor = 0;
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lt = &offsets.left_top;
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lb = &offsets.left_bottom;
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rt = &offsets.right_top;
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rb = &offsets.right_bottom;
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x_div = frm->fmt->x_div;
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y_div = frm->fmt->y_div;
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uv_factor = frm->fmt->uv_factor;
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uv_stride = frm->stride / x_div;
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pixel_width = frm->stride / frm->width;
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lt->y_off = y * frm->stride + x * pixel_width;
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lt->u_off =
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frm->width * frm->height + (y / y_div) * uv_stride + x / x_div;
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lt->v_off = lt->u_off + frm->width * frm->height / uv_factor;
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lb->y_off = lt->y_off + (h - 1) * frm->stride;
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lb->u_off = lt->u_off + (h / y_div - 1) * uv_stride;
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lb->v_off = lt->v_off + (h / y_div - 1) * uv_stride;
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rt->y_off = lt->y_off + (w - 1) * pixel_width;
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rt->u_off = lt->u_off + w / x_div - 1;
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rt->v_off = lt->v_off + w / x_div - 1;
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rb->y_off = lb->y_off + (w - 1) * pixel_width;
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rb->u_off = lb->u_off + w / x_div - 1;
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rb->v_off = lb->v_off + w / x_div - 1;
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return offsets;
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}
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static struct rga_addr_offset *rga_lookup_draw_pos(struct
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rga_corners_addr_offset
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* offsets, u32 rotate_mode,
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u32 mirr_mode)
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{
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static enum e_rga_start_pos rot_mir_point_matrix[4][4] = {
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{
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LT, RT, LB, RB,
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},
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{
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RT, LT, RB, LB,
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},
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{
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RB, LB, RT, LT,
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},
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{
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LB, RB, LT, RT,
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},
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};
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if (!offsets)
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return NULL;
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switch (rot_mir_point_matrix[rotate_mode][mirr_mode]) {
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case LT:
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return &offsets->left_top;
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case LB:
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return &offsets->left_bottom;
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case RT:
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return &offsets->right_top;
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case RB:
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return &offsets->right_bottom;
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}
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return NULL;
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}
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static void rga_cmd_set_src_addr(struct rga_ctx *ctx, void *mmu_pages)
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{
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struct rockchip_rga *rga = ctx->rga;
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u32 *dest = rga->cmdbuf_virt;
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unsigned int reg;
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reg = RGA_MMU_SRC_BASE - RGA_MODE_BASE_REG;
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dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
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reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
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dest[reg >> 2] |= 0x7;
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}
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static void rga_cmd_set_src1_addr(struct rga_ctx *ctx, void *mmu_pages)
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{
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struct rockchip_rga *rga = ctx->rga;
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u32 *dest = rga->cmdbuf_virt;
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unsigned int reg;
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reg = RGA_MMU_SRC1_BASE - RGA_MODE_BASE_REG;
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dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
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reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
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dest[reg >> 2] |= 0x7 << 4;
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}
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static void rga_cmd_set_dst_addr(struct rga_ctx *ctx, void *mmu_pages)
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{
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struct rockchip_rga *rga = ctx->rga;
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u32 *dest = rga->cmdbuf_virt;
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unsigned int reg;
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reg = RGA_MMU_DST_BASE - RGA_MODE_BASE_REG;
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dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
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reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
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dest[reg >> 2] |= 0x7 << 8;
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}
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static void rga_cmd_set_trans_info(struct rga_ctx *ctx)
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{
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struct rockchip_rga *rga = ctx->rga;
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u32 *dest = rga->cmdbuf_virt;
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unsigned int scale_dst_w, scale_dst_h;
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unsigned int src_h, src_w, src_x, src_y, dst_h, dst_w, dst_x, dst_y;
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union rga_src_info src_info;
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union rga_dst_info dst_info;
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union rga_src_x_factor x_factor;
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union rga_src_y_factor y_factor;
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union rga_src_vir_info src_vir_info;
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union rga_src_act_info src_act_info;
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union rga_dst_vir_info dst_vir_info;
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union rga_dst_act_info dst_act_info;
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struct rga_addr_offset *dst_offset;
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struct rga_corners_addr_offset offsets;
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struct rga_corners_addr_offset src_offsets;
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src_h = ctx->in.crop.height;
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src_w = ctx->in.crop.width;
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src_x = ctx->in.crop.left;
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src_y = ctx->in.crop.top;
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dst_h = ctx->out.crop.height;
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dst_w = ctx->out.crop.width;
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dst_x = ctx->out.crop.left;
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dst_y = ctx->out.crop.top;
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src_info.val = dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2];
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dst_info.val = dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2];
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x_factor.val = dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2];
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y_factor.val = dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2];
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src_vir_info.val = dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2];
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src_act_info.val = dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2];
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dst_vir_info.val = dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2];
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dst_act_info.val = dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2];
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src_info.data.format = ctx->in.fmt->hw_format;
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src_info.data.swap = ctx->in.fmt->color_swap;
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dst_info.data.format = ctx->out.fmt->hw_format;
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dst_info.data.swap = ctx->out.fmt->color_swap;
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/*
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* CSC mode must only be set when the colorspace families differ between
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* input and output. It must remain unset (zeroed) if both are the same.
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*/
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if (RGA_COLOR_FMT_IS_YUV(ctx->in.fmt->hw_format) &&
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RGA_COLOR_FMT_IS_RGB(ctx->out.fmt->hw_format)) {
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switch (ctx->in.colorspace) {
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case V4L2_COLORSPACE_REC709:
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src_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0;
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break;
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default:
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src_info.data.csc_mode = RGA_SRC_CSC_MODE_BT601_R0;
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break;
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}
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}
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if (RGA_COLOR_FMT_IS_RGB(ctx->in.fmt->hw_format) &&
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RGA_COLOR_FMT_IS_YUV(ctx->out.fmt->hw_format)) {
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switch (ctx->out.colorspace) {
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case V4L2_COLORSPACE_REC709:
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dst_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0;
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break;
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default:
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dst_info.data.csc_mode = RGA_DST_CSC_MODE_BT601_R0;
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break;
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}
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}
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if (ctx->vflip)
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src_info.data.mir_mode |= RGA_SRC_MIRR_MODE_X;
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if (ctx->hflip)
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src_info.data.mir_mode |= RGA_SRC_MIRR_MODE_Y;
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switch (ctx->rotate) {
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case 90:
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src_info.data.rot_mode = RGA_SRC_ROT_MODE_90_DEGREE;
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break;
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case 180:
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src_info.data.rot_mode = RGA_SRC_ROT_MODE_180_DEGREE;
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break;
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case 270:
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src_info.data.rot_mode = RGA_SRC_ROT_MODE_270_DEGREE;
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break;
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default:
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src_info.data.rot_mode = RGA_SRC_ROT_MODE_0_DEGREE;
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break;
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}
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/*
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* Calculate the up/down scaling mode/factor.
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*
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* RGA used to scale the picture first, and then rotate second,
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* so we need to swap the w/h when rotate degree is 90/270.
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*/
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if (src_info.data.rot_mode == RGA_SRC_ROT_MODE_90_DEGREE ||
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src_info.data.rot_mode == RGA_SRC_ROT_MODE_270_DEGREE) {
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if (rga->version.major == 0 || rga->version.minor == 0) {
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if (dst_w == src_h)
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src_h -= 8;
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if (abs(src_w - dst_h) < 16)
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src_w -= 16;
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}
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scale_dst_h = dst_w;
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scale_dst_w = dst_h;
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} else {
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scale_dst_w = dst_w;
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scale_dst_h = dst_h;
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}
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if (src_w == scale_dst_w) {
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src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_NO;
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x_factor.val = 0;
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} else if (src_w > scale_dst_w) {
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src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_DOWN;
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x_factor.data.down_scale_factor =
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rga_get_scaling(src_w, scale_dst_w) + 1;
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} else {
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src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_UP;
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x_factor.data.up_scale_factor =
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rga_get_scaling(src_w - 1, scale_dst_w - 1);
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}
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if (src_h == scale_dst_h) {
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src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_NO;
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y_factor.val = 0;
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} else if (src_h > scale_dst_h) {
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src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_DOWN;
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y_factor.data.down_scale_factor =
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rga_get_scaling(src_h, scale_dst_h) + 1;
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} else {
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src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_UP;
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y_factor.data.up_scale_factor =
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rga_get_scaling(src_h - 1, scale_dst_h - 1);
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}
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/*
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* Calculate the framebuffer virtual strides and active size,
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* note that the step of vir_stride / vir_width is 4 byte words
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*/
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src_vir_info.data.vir_stride = ctx->in.stride >> 2;
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src_vir_info.data.vir_width = ctx->in.stride >> 2;
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src_act_info.data.act_height = src_h - 1;
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src_act_info.data.act_width = src_w - 1;
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dst_vir_info.data.vir_stride = ctx->out.stride >> 2;
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dst_act_info.data.act_height = dst_h - 1;
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dst_act_info.data.act_width = dst_w - 1;
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/*
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* Calculate the source framebuffer base address with offset pixel.
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*/
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src_offsets = rga_get_addr_offset(&ctx->in, src_x, src_y,
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src_w, src_h);
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/*
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* Configure the dest framebuffer base address with pixel offset.
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*/
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offsets = rga_get_addr_offset(&ctx->out, dst_x, dst_y, dst_w, dst_h);
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dst_offset = rga_lookup_draw_pos(&offsets, src_info.data.rot_mode,
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src_info.data.mir_mode);
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dest[(RGA_SRC_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
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src_offsets.left_top.y_off;
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dest[(RGA_SRC_CB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
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src_offsets.left_top.u_off;
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dest[(RGA_SRC_CR_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
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src_offsets.left_top.v_off;
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dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2] = x_factor.val;
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dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2] = y_factor.val;
|
||
|
|
dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = src_vir_info.val;
|
||
|
|
dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = src_act_info.val;
|
||
|
|
|
||
|
|
dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2] = src_info.val;
|
||
|
|
|
||
|
|
dest[(RGA_DST_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
|
||
|
|
dst_offset->y_off;
|
||
|
|
dest[(RGA_DST_CB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
|
||
|
|
dst_offset->u_off;
|
||
|
|
dest[(RGA_DST_CR_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
|
||
|
|
dst_offset->v_off;
|
||
|
|
|
||
|
|
dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = dst_vir_info.val;
|
||
|
|
dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = dst_act_info.val;
|
||
|
|
|
||
|
|
dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2] = dst_info.val;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void rga_cmd_set_mode(struct rga_ctx *ctx)
|
||
|
|
{
|
||
|
|
struct rockchip_rga *rga = ctx->rga;
|
||
|
|
u32 *dest = rga->cmdbuf_virt;
|
||
|
|
union rga_mode_ctrl mode;
|
||
|
|
union rga_alpha_ctrl0 alpha_ctrl0;
|
||
|
|
union rga_alpha_ctrl1 alpha_ctrl1;
|
||
|
|
|
||
|
|
mode.val = 0;
|
||
|
|
alpha_ctrl0.val = 0;
|
||
|
|
alpha_ctrl1.val = 0;
|
||
|
|
|
||
|
|
mode.data.gradient_sat = 1;
|
||
|
|
mode.data.render = RGA_MODE_RENDER_BITBLT;
|
||
|
|
mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
|
||
|
|
|
||
|
|
/* disable alpha blending */
|
||
|
|
dest[(RGA_ALPHA_CTRL0 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl0.val;
|
||
|
|
dest[(RGA_ALPHA_CTRL1 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl1.val;
|
||
|
|
|
||
|
|
dest[(RGA_MODE_CTRL - RGA_MODE_BASE_REG) >> 2] = mode.val;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void rga_cmd_set(struct rga_ctx *ctx)
|
||
|
|
{
|
||
|
|
struct rockchip_rga *rga = ctx->rga;
|
||
|
|
|
||
|
|
memset(rga->cmdbuf_virt, 0, RGA_CMDBUF_SIZE * 4);
|
||
|
|
|
||
|
|
rga_cmd_set_src_addr(ctx, rga->src_mmu_pages);
|
||
|
|
/*
|
||
|
|
* Due to hardware bug,
|
||
|
|
* src1 mmu also should be configured when using alpha blending.
|
||
|
|
*/
|
||
|
|
rga_cmd_set_src1_addr(ctx, rga->dst_mmu_pages);
|
||
|
|
|
||
|
|
rga_cmd_set_dst_addr(ctx, rga->dst_mmu_pages);
|
||
|
|
rga_cmd_set_mode(ctx);
|
||
|
|
|
||
|
|
rga_cmd_set_trans_info(ctx);
|
||
|
|
|
||
|
|
rga_write(rga, RGA_CMD_BASE, rga->cmdbuf_phy);
|
||
|
|
|
||
|
|
/* sync CMD buf for RGA */
|
||
|
|
dma_sync_single_for_device(rga->dev, rga->cmdbuf_phy,
|
||
|
|
PAGE_SIZE, DMA_BIDIRECTIONAL);
|
||
|
|
}
|
||
|
|
|
||
|
|
void rga_hw_start(struct rockchip_rga *rga)
|
||
|
|
{
|
||
|
|
struct rga_ctx *ctx = rga->curr;
|
||
|
|
|
||
|
|
rga_cmd_set(ctx);
|
||
|
|
|
||
|
|
rga_write(rga, RGA_SYS_CTRL, 0x00);
|
||
|
|
|
||
|
|
rga_write(rga, RGA_SYS_CTRL, 0x22);
|
||
|
|
|
||
|
|
rga_write(rga, RGA_INT, 0x600);
|
||
|
|
|
||
|
|
rga_write(rga, RGA_CMD_CTRL, 0x1);
|
||
|
|
}
|