313 lines
9.8 KiB
C
313 lines
9.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2022 Richtek Technology Corp.
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*
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* Author: ChiYuan Huang <cy_huang@richtek.com>
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*/
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/core.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include "mt6370.h"
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#define MT6370_REG_DEV_INFO 0x100
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#define MT6370_REG_CHG_IRQ1 0x1C0
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#define MT6370_REG_CHG_MASK1 0x1E0
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#define MT6370_REG_MAXADDR 0x1FF
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#define MT6370_VENID_MASK GENMASK(7, 4)
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#define MT6370_NUM_IRQREGS 16
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#define MT6370_USBC_I2CADDR 0x4E
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#define MT6370_MAX_ADDRLEN 2
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#define MT6370_VENID_RT5081 0x8
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#define MT6370_VENID_RT5081A 0xA
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#define MT6370_VENID_MT6370 0xE
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#define MT6370_VENID_MT6371 0xF
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#define MT6370_VENID_MT6372P 0x9
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#define MT6370_VENID_MT6372CP 0xB
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static const struct regmap_irq mt6370_irqs[] = {
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_DIRCHGON, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_TREG, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_AICR, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_MIVR, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_PWR_RDY, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_FL_CHG_VINOVP, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_VSYSUV, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_VSYSOV, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_VBATOV, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_VINOVPCHG, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_TS_BAT_COLD, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_TS_BAT_COOL, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_TS_BAT_WARM, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_TS_BAT_HOT, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_TS_STATC, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_FAULT, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_STATC, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_TMR, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_BATABS, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_ADPBAD, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_RVP, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_TSHUTDOWN, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_IINMEAS, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_ICCMEAS, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHGDET_DONE, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_WDTMR, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_SSFINISH, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_RECHG, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_TERM, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_IEOC, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_ADC_DONE, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_PUMPX_DONE, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_BST_BATUV, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_BST_MIDOV, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_BST_OLP, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_ATTACH, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_DETACH, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_HVDCP_STPDONE, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_HVDCP_VBUSDET_DONE, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_HVDCP_DET, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHGDET, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_DCDT, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_DIRCHG_VGOK, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_DIRCHG_WDTMR, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_DIRCHG_UC, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_DIRCHG_OC, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_DIRCHG_OV, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_OVPCTRL_SWON, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_OVPCTRL_UVP_D, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_OVPCTRL_UVP, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_OVPCTRL_OVP_D, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_OVPCTRL_OVP, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED_STRBPIN, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED_TORPIN, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED_TX, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED_LVF, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED2_SHORT, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED1_SHORT, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED2_STRB, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED1_STRB, 8),
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REGMAP_IRQ_REG_LINE(mT6370_IRQ_FLED2_STRB_TO, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED1_STRB_TO, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED2_TOR, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED1_TOR, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_OTP, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_VDDA_OVP, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_VDDA_UV, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_LDO_OC, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_BLED_OCP, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_BLED_OVP, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_DSV_VNEG_OCP, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_DSV_VPOS_OCP, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_DSV_BST_OCP, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_DSV_VNEG_SCP, 8),
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REGMAP_IRQ_REG_LINE(MT6370_IRQ_DSV_VPOS_SCP, 8),
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};
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static const struct regmap_irq_chip mt6370_irq_chip = {
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.name = "mt6370-irqs",
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.status_base = MT6370_REG_CHG_IRQ1,
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.mask_base = MT6370_REG_CHG_MASK1,
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.num_regs = MT6370_NUM_IRQREGS,
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.irqs = mt6370_irqs,
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.num_irqs = ARRAY_SIZE(mt6370_irqs),
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};
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static const struct resource mt6370_regulator_irqs[] = {
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DEFINE_RES_IRQ_NAMED(MT6370_IRQ_DSV_VPOS_SCP, "db_vpos_scp"),
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DEFINE_RES_IRQ_NAMED(MT6370_IRQ_DSV_VNEG_SCP, "db_vneg_scp"),
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DEFINE_RES_IRQ_NAMED(MT6370_IRQ_DSV_BST_OCP, "db_vbst_ocp"),
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DEFINE_RES_IRQ_NAMED(MT6370_IRQ_DSV_VPOS_OCP, "db_vpos_ocp"),
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DEFINE_RES_IRQ_NAMED(MT6370_IRQ_DSV_VNEG_OCP, "db_vneg_ocp"),
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DEFINE_RES_IRQ_NAMED(MT6370_IRQ_LDO_OC, "ldo_oc"),
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};
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static const struct mfd_cell mt6370_devices[] = {
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MFD_CELL_OF("mt6370-adc",
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NULL, NULL, 0, 0, "mediatek,mt6370-adc"),
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MFD_CELL_OF("mt6370-charger",
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NULL, NULL, 0, 0, "mediatek,mt6370-charger"),
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MFD_CELL_OF("mt6370-flashlight",
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NULL, NULL, 0, 0, "mediatek,mt6370-flashlight"),
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MFD_CELL_OF("mt6370-indicator",
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NULL, NULL, 0, 0, "mediatek,mt6370-indicator"),
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MFD_CELL_OF("mt6370-tcpc",
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NULL, NULL, 0, 0, "mediatek,mt6370-tcpc"),
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MFD_CELL_RES("mt6370-regulator", mt6370_regulator_irqs),
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};
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static const struct mfd_cell mt6370_exclusive_devices[] = {
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MFD_CELL_OF("mt6370-backlight",
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NULL, NULL, 0, 0, "mediatek,mt6370-backlight"),
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};
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static const struct mfd_cell mt6372_exclusive_devices[] = {
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MFD_CELL_OF("mt6370-backlight",
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NULL, NULL, 0, 0, "mediatek,mt6372-backlight"),
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};
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static int mt6370_check_vendor_info(struct device *dev, struct regmap *rmap,
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int *vid)
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{
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unsigned int devinfo;
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int ret;
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ret = regmap_read(rmap, MT6370_REG_DEV_INFO, &devinfo);
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if (ret)
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return ret;
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*vid = FIELD_GET(MT6370_VENID_MASK, devinfo);
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switch (*vid) {
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case MT6370_VENID_RT5081:
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case MT6370_VENID_RT5081A:
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case MT6370_VENID_MT6370:
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case MT6370_VENID_MT6371:
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case MT6370_VENID_MT6372P:
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case MT6370_VENID_MT6372CP:
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return 0;
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default:
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dev_err(dev, "Unknown Vendor ID 0x%02x\n", devinfo);
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return -ENODEV;
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}
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}
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static int mt6370_regmap_read(void *context, const void *reg_buf,
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size_t reg_size, void *val_buf, size_t val_size)
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{
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struct mt6370_info *info = context;
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const u8 *u8_buf = reg_buf;
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u8 bank_idx, bank_addr;
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int ret;
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bank_idx = u8_buf[0];
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bank_addr = u8_buf[1];
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ret = i2c_smbus_read_i2c_block_data(info->i2c[bank_idx], bank_addr,
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val_size, val_buf);
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if (ret < 0)
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return ret;
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if (ret != val_size)
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return -EIO;
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return 0;
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}
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static int mt6370_regmap_write(void *context, const void *data, size_t count)
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{
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struct mt6370_info *info = context;
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const u8 *u8_buf = data;
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u8 bank_idx, bank_addr;
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int len = count - MT6370_MAX_ADDRLEN;
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bank_idx = u8_buf[0];
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bank_addr = u8_buf[1];
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return i2c_smbus_write_i2c_block_data(info->i2c[bank_idx], bank_addr,
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len, data + MT6370_MAX_ADDRLEN);
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}
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static const struct regmap_bus mt6370_regmap_bus = {
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.read = mt6370_regmap_read,
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.write = mt6370_regmap_write,
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};
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static const struct regmap_config mt6370_regmap_config = {
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.reg_bits = 16,
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.val_bits = 8,
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.reg_format_endian = REGMAP_ENDIAN_BIG,
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.max_register = MT6370_REG_MAXADDR,
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};
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static int mt6370_probe(struct i2c_client *i2c)
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{
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struct mt6370_info *info;
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struct i2c_client *usbc_i2c;
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struct regmap *regmap;
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struct device *dev = &i2c->dev;
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int ret, vid;
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info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
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if (!info)
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return -ENOMEM;
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usbc_i2c = devm_i2c_new_dummy_device(dev, i2c->adapter,
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MT6370_USBC_I2CADDR);
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if (IS_ERR(usbc_i2c))
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return dev_err_probe(dev, PTR_ERR(usbc_i2c),
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"Failed to register USBC I2C client\n");
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/* Assign I2C client for PMU and TypeC */
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info->i2c[MT6370_PMU_I2C] = i2c;
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info->i2c[MT6370_USBC_I2C] = usbc_i2c;
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regmap = devm_regmap_init(dev, &mt6370_regmap_bus,
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info, &mt6370_regmap_config);
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if (IS_ERR(regmap))
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return dev_err_probe(dev, PTR_ERR(regmap),
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"Failed to init regmap\n");
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ret = mt6370_check_vendor_info(dev, regmap, &vid);
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if (ret)
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return dev_err_probe(dev, ret, "Failed to check vendor info\n");
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ret = devm_regmap_add_irq_chip(dev, regmap, i2c->irq,
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IRQF_ONESHOT, -1, &mt6370_irq_chip,
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&info->irq_data);
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if (ret)
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return dev_err_probe(dev, ret, "Failed to add irq chip\n");
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switch (vid) {
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case MT6370_VENID_MT6372P:
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case MT6370_VENID_MT6372CP:
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ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO,
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mt6372_exclusive_devices,
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ARRAY_SIZE(mt6372_exclusive_devices),
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NULL, 0,
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regmap_irq_get_domain(info->irq_data));
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break;
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default:
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ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO,
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mt6370_exclusive_devices,
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ARRAY_SIZE(mt6370_exclusive_devices),
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NULL, 0,
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regmap_irq_get_domain(info->irq_data));
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break;
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}
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if (ret)
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return dev_err_probe(dev, ret, "Failed to add the exclusive devices\n");
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return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO,
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mt6370_devices, ARRAY_SIZE(mt6370_devices),
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NULL, 0,
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regmap_irq_get_domain(info->irq_data));
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}
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static const struct of_device_id mt6370_match_table[] = {
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{ .compatible = "mediatek,mt6370" },
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, mt6370_match_table);
|
||
|
|
|
||
|
|
static struct i2c_driver mt6370_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "mt6370",
|
||
|
|
.of_match_table = mt6370_match_table,
|
||
|
|
},
|
||
|
|
.probe_new = mt6370_probe,
|
||
|
|
};
|
||
|
|
module_i2c_driver(mt6370_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
|
||
|
|
MODULE_DESCRIPTION("MediaTek MT6370 SubPMIC Driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|