332 lines
8.3 KiB
C
332 lines
8.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* sdhci-pci-arasan.c - Driver for Arasan PCI Controller with
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* integrated phy.
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*
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* Copyright (C) 2017 Arasan Chip Systems Inc.
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*
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* Author: Atul Garg <agarg@arasan.com>
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*/
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include "sdhci.h"
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#include "sdhci-pci.h"
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/* Extra registers for Arasan SD/SDIO/MMC Host Controller with PHY */
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#define PHY_ADDR_REG 0x300
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#define PHY_DAT_REG 0x304
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#define PHY_WRITE BIT(8)
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#define PHY_BUSY BIT(9)
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#define DATA_MASK 0xFF
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/* PHY Specific Registers */
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#define DLL_STATUS 0x00
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#define IPAD_CTRL1 0x01
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#define IPAD_CTRL2 0x02
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#define IPAD_STS 0x03
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#define IOREN_CTRL1 0x06
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#define IOREN_CTRL2 0x07
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#define IOPU_CTRL1 0x08
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#define IOPU_CTRL2 0x09
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#define ITAP_DELAY 0x0C
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#define OTAP_DELAY 0x0D
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#define STRB_SEL 0x0E
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#define CLKBUF_SEL 0x0F
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#define MODE_CTRL 0x11
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#define DLL_TRIM 0x12
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#define CMD_CTRL 0x20
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#define DATA_CTRL 0x21
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#define STRB_CTRL 0x22
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#define CLK_CTRL 0x23
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#define PHY_CTRL 0x24
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#define DLL_ENBL BIT(3)
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#define RTRIM_EN BIT(1)
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#define PDB_ENBL BIT(1)
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#define RETB_ENBL BIT(6)
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#define ODEN_CMD BIT(1)
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#define ODEN_DAT 0xFF
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#define REN_STRB BIT(0)
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#define REN_CMND BIT(1)
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#define REN_DATA 0xFF
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#define PU_CMD BIT(1)
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#define PU_DAT 0xFF
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#define ITAPDLY_EN BIT(0)
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#define OTAPDLY_EN BIT(0)
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#define OD_REL_CMD BIT(1)
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#define OD_REL_DAT 0xFF
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#define DLLTRM_ICP 0x8
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#define PDB_CMND BIT(0)
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#define PDB_DATA 0xFF
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#define PDB_STRB BIT(0)
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#define PDB_CLOCK BIT(0)
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#define CALDONE_MASK 0x10
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#define DLL_RDY_MASK 0x10
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#define MAX_CLK_BUF 0x7
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/* Mode Controls */
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#define ENHSTRB_MODE BIT(0)
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#define HS400_MODE BIT(1)
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#define LEGACY_MODE BIT(2)
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#define DDR50_MODE BIT(3)
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/*
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* Controller has no specific bits for HS200/HS.
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* Used BIT(4), BIT(5) for software programming.
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*/
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#define HS200_MODE BIT(4)
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#define HISPD_MODE BIT(5)
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#define OTAPDLY(x) (((x) << 1) | OTAPDLY_EN)
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#define ITAPDLY(x) (((x) << 1) | ITAPDLY_EN)
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#define FREQSEL(x) (((x) << 5) | DLL_ENBL)
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#define IOPAD(x, y) ((x) | ((y) << 2))
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/* Arasan private data */
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struct arasan_host {
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u32 chg_clk;
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};
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static int arasan_phy_addr_poll(struct sdhci_host *host, u32 offset, u32 mask)
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{
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ktime_t timeout = ktime_add_us(ktime_get(), 100);
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bool failed;
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u8 val = 0;
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while (1) {
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failed = ktime_after(ktime_get(), timeout);
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val = sdhci_readw(host, PHY_ADDR_REG);
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if (!(val & mask))
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return 0;
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if (failed)
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return -EBUSY;
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}
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}
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static int arasan_phy_write(struct sdhci_host *host, u8 data, u8 offset)
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{
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sdhci_writew(host, data, PHY_DAT_REG);
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sdhci_writew(host, (PHY_WRITE | offset), PHY_ADDR_REG);
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return arasan_phy_addr_poll(host, PHY_ADDR_REG, PHY_BUSY);
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}
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static int arasan_phy_read(struct sdhci_host *host, u8 offset, u8 *data)
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{
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int ret;
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sdhci_writew(host, 0, PHY_DAT_REG);
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sdhci_writew(host, offset, PHY_ADDR_REG);
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ret = arasan_phy_addr_poll(host, PHY_ADDR_REG, PHY_BUSY);
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/* Masking valid data bits */
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*data = sdhci_readw(host, PHY_DAT_REG) & DATA_MASK;
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return ret;
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}
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static int arasan_phy_sts_poll(struct sdhci_host *host, u32 offset, u32 mask)
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{
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int ret;
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ktime_t timeout = ktime_add_us(ktime_get(), 100);
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bool failed;
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u8 val = 0;
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while (1) {
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failed = ktime_after(ktime_get(), timeout);
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ret = arasan_phy_read(host, offset, &val);
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if (ret)
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return -EBUSY;
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else if (val & mask)
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return 0;
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if (failed)
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return -EBUSY;
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}
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}
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/* Initialize the Arasan PHY */
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static int arasan_phy_init(struct sdhci_host *host)
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{
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int ret;
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u8 val;
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/* Program IOPADs and wait for calibration to be done */
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if (arasan_phy_read(host, IPAD_CTRL1, &val) ||
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arasan_phy_write(host, val | RETB_ENBL | PDB_ENBL, IPAD_CTRL1) ||
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arasan_phy_read(host, IPAD_CTRL2, &val) ||
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arasan_phy_write(host, val | RTRIM_EN, IPAD_CTRL2))
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return -EBUSY;
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ret = arasan_phy_sts_poll(host, IPAD_STS, CALDONE_MASK);
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if (ret)
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return -EBUSY;
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/* Program CMD/Data lines */
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if (arasan_phy_read(host, IOREN_CTRL1, &val) ||
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arasan_phy_write(host, val | REN_CMND | REN_STRB, IOREN_CTRL1) ||
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arasan_phy_read(host, IOPU_CTRL1, &val) ||
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arasan_phy_write(host, val | PU_CMD, IOPU_CTRL1) ||
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arasan_phy_read(host, CMD_CTRL, &val) ||
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arasan_phy_write(host, val | PDB_CMND, CMD_CTRL) ||
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arasan_phy_read(host, IOREN_CTRL2, &val) ||
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arasan_phy_write(host, val | REN_DATA, IOREN_CTRL2) ||
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arasan_phy_read(host, IOPU_CTRL2, &val) ||
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arasan_phy_write(host, val | PU_DAT, IOPU_CTRL2) ||
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arasan_phy_read(host, DATA_CTRL, &val) ||
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arasan_phy_write(host, val | PDB_DATA, DATA_CTRL) ||
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arasan_phy_read(host, STRB_CTRL, &val) ||
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arasan_phy_write(host, val | PDB_STRB, STRB_CTRL) ||
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arasan_phy_read(host, CLK_CTRL, &val) ||
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arasan_phy_write(host, val | PDB_CLOCK, CLK_CTRL) ||
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arasan_phy_read(host, CLKBUF_SEL, &val) ||
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arasan_phy_write(host, val | MAX_CLK_BUF, CLKBUF_SEL) ||
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arasan_phy_write(host, LEGACY_MODE, MODE_CTRL))
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return -EBUSY;
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return 0;
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}
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/* Set Arasan PHY for different modes */
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static int arasan_phy_set(struct sdhci_host *host, u8 mode, u8 otap,
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u8 drv_type, u8 itap, u8 trim, u8 clk)
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{
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u8 val;
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int ret;
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if (mode == HISPD_MODE || mode == HS200_MODE)
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ret = arasan_phy_write(host, 0x0, MODE_CTRL);
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else
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ret = arasan_phy_write(host, mode, MODE_CTRL);
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if (ret)
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return ret;
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if (mode == HS400_MODE || mode == HS200_MODE) {
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ret = arasan_phy_read(host, IPAD_CTRL1, &val);
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if (ret)
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return ret;
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ret = arasan_phy_write(host, IOPAD(val, drv_type), IPAD_CTRL1);
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if (ret)
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return ret;
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}
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if (mode == LEGACY_MODE) {
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ret = arasan_phy_write(host, 0x0, OTAP_DELAY);
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if (ret)
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return ret;
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ret = arasan_phy_write(host, 0x0, ITAP_DELAY);
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} else {
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ret = arasan_phy_write(host, OTAPDLY(otap), OTAP_DELAY);
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if (ret)
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return ret;
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if (mode != HS200_MODE)
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ret = arasan_phy_write(host, ITAPDLY(itap), ITAP_DELAY);
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else
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ret = arasan_phy_write(host, 0x0, ITAP_DELAY);
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}
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if (ret)
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return ret;
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if (mode != LEGACY_MODE) {
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ret = arasan_phy_write(host, trim, DLL_TRIM);
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if (ret)
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return ret;
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}
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ret = arasan_phy_write(host, 0, DLL_STATUS);
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if (ret)
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return ret;
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if (mode != LEGACY_MODE) {
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ret = arasan_phy_write(host, FREQSEL(clk), DLL_STATUS);
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if (ret)
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return ret;
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ret = arasan_phy_sts_poll(host, DLL_STATUS, DLL_RDY_MASK);
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if (ret)
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return -EBUSY;
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}
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return 0;
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}
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static int arasan_select_phy_clock(struct sdhci_host *host)
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{
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struct sdhci_pci_slot *slot = sdhci_priv(host);
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struct arasan_host *arasan_host = sdhci_pci_priv(slot);
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u8 clk;
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if (arasan_host->chg_clk == host->mmc->ios.clock)
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return 0;
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arasan_host->chg_clk = host->mmc->ios.clock;
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if (host->mmc->ios.clock == 200000000)
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clk = 0x0;
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else if (host->mmc->ios.clock == 100000000)
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clk = 0x2;
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else if (host->mmc->ios.clock == 50000000)
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clk = 0x1;
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else
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clk = 0x0;
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if (host->mmc_host_ops.hs400_enhanced_strobe) {
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arasan_phy_set(host, ENHSTRB_MODE, 1, 0x0, 0x0,
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DLLTRM_ICP, clk);
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} else {
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switch (host->mmc->ios.timing) {
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case MMC_TIMING_LEGACY:
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arasan_phy_set(host, LEGACY_MODE, 0x0, 0x0, 0x0,
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0x0, 0x0);
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break;
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case MMC_TIMING_MMC_HS:
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case MMC_TIMING_SD_HS:
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arasan_phy_set(host, HISPD_MODE, 0x3, 0x0, 0x2,
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DLLTRM_ICP, clk);
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break;
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case MMC_TIMING_MMC_HS200:
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case MMC_TIMING_UHS_SDR104:
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arasan_phy_set(host, HS200_MODE, 0x2,
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host->mmc->ios.drv_type, 0x0,
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DLLTRM_ICP, clk);
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break;
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case MMC_TIMING_MMC_DDR52:
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case MMC_TIMING_UHS_DDR50:
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arasan_phy_set(host, DDR50_MODE, 0x1, 0x0,
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0x0, DLLTRM_ICP, clk);
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break;
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case MMC_TIMING_MMC_HS400:
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arasan_phy_set(host, HS400_MODE, 0x1,
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host->mmc->ios.drv_type, 0xa,
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DLLTRM_ICP, clk);
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break;
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default:
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break;
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}
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}
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return 0;
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}
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static int arasan_pci_probe_slot(struct sdhci_pci_slot *slot)
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{
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int err;
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slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | MMC_CAP_8_BIT_DATA;
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err = arasan_phy_init(slot->host);
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if (err)
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return -ENODEV;
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return 0;
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}
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static void arasan_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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sdhci_set_clock(host, clock);
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/* Change phy settings for the new clock */
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arasan_select_phy_clock(host);
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}
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static const struct sdhci_ops arasan_sdhci_pci_ops = {
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.set_clock = arasan_sdhci_set_clock,
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.enable_dma = sdhci_pci_enable_dma,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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const struct sdhci_pci_fixes sdhci_arasan = {
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.probe_slot = arasan_pci_probe_slot,
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.ops = &arasan_sdhci_pci_ops,
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.priv_size = sizeof(struct arasan_host),
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};
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