708 lines
17 KiB
C
708 lines
17 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Microchip switch driver common header
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*
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* Copyright (C) 2017-2019 Microchip Technology Inc.
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*/
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#ifndef __KSZ_COMMON_H
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#define __KSZ_COMMON_H
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#include <linux/etherdevice.h>
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#include <linux/kernel.h>
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#include <linux/mutex.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <net/dsa.h>
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#include <linux/irq.h>
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#include "ksz_ptp.h"
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#define KSZ_MAX_NUM_PORTS 8
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struct ksz_device;
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struct ksz_port;
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struct vlan_table {
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u32 table[3];
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};
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struct ksz_port_mib {
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struct mutex cnt_mutex; /* structure access */
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u8 cnt_ptr;
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u64 *counters;
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struct rtnl_link_stats64 stats64;
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struct ethtool_pause_stats pause_stats;
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struct spinlock stats64_lock;
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};
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struct ksz_mib_names {
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int index;
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char string[ETH_GSTRING_LEN];
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};
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struct ksz_chip_data {
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u32 chip_id;
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const char *dev_name;
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int num_vlans;
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int num_alus;
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int num_statics;
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int cpu_ports;
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int port_cnt;
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u8 port_nirqs;
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u8 num_tx_queues;
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bool tc_cbs_supported;
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const struct ksz_dev_ops *ops;
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bool phy_errata_9477;
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bool ksz87xx_eee_link_erratum;
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const struct ksz_mib_names *mib_names;
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int mib_cnt;
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u8 reg_mib_cnt;
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const u16 *regs;
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const u32 *masks;
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const u8 *shifts;
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const u8 *xmii_ctrl0;
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const u8 *xmii_ctrl1;
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int stp_ctrl_reg;
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int broadcast_ctrl_reg;
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int multicast_ctrl_reg;
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int start_ctrl_reg;
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bool supports_mii[KSZ_MAX_NUM_PORTS];
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bool supports_rmii[KSZ_MAX_NUM_PORTS];
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bool supports_rgmii[KSZ_MAX_NUM_PORTS];
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bool internal_phy[KSZ_MAX_NUM_PORTS];
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bool gbit_capable[KSZ_MAX_NUM_PORTS];
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const struct regmap_access_table *wr_table;
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const struct regmap_access_table *rd_table;
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};
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struct ksz_irq {
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u16 masked;
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u16 reg_mask;
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u16 reg_status;
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struct irq_domain *domain;
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int nirqs;
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int irq_num;
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char name[16];
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struct ksz_device *dev;
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};
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struct ksz_ptp_irq {
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struct ksz_port *port;
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u16 ts_reg;
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bool ts_en;
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char name[16];
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int num;
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};
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struct ksz_port {
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bool remove_tag; /* Remove Tag flag set, for ksz8795 only */
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bool learning;
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int stp_state;
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struct phy_device phydev;
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u32 on:1; /* port is not disabled by hardware */
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u32 fiber:1; /* port is fiber */
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u32 force:1;
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u32 read:1; /* read MIB counters in background */
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u32 freeze:1; /* MIB counter freeze is enabled */
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struct ksz_port_mib mib;
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phy_interface_t interface;
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u32 rgmii_tx_val;
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u32 rgmii_rx_val;
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struct ksz_device *ksz_dev;
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struct ksz_irq pirq;
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u8 num;
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#if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP)
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struct hwtstamp_config tstamp_config;
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bool hwts_tx_en;
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bool hwts_rx_en;
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struct ksz_irq ptpirq;
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struct ksz_ptp_irq ptpmsg_irq[3];
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ktime_t tstamp_msg;
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struct completion tstamp_msg_comp;
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#endif
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};
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struct ksz_device {
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struct dsa_switch *ds;
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struct ksz_platform_data *pdata;
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const struct ksz_chip_data *info;
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struct mutex dev_mutex; /* device access */
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struct mutex regmap_mutex; /* regmap access */
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struct mutex alu_mutex; /* ALU access */
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struct mutex vlan_mutex; /* vlan access */
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const struct ksz_dev_ops *dev_ops;
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struct device *dev;
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struct regmap *regmap[3];
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void *priv;
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int irq;
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struct gpio_desc *reset_gpio; /* Optional reset GPIO */
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/* chip specific data */
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u32 chip_id;
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u8 chip_rev;
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int cpu_port; /* port connected to CPU */
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int phy_port_cnt;
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phy_interface_t compat_interface;
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bool synclko_125;
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bool synclko_disable;
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struct vlan_table *vlan_cache;
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struct ksz_port *ports;
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struct delayed_work mib_read;
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unsigned long mib_read_interval;
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u16 mirror_rx;
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u16 mirror_tx;
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u16 port_mask;
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struct mutex lock_irq; /* IRQ Access */
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struct ksz_irq girq;
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struct ksz_ptp_data ptp_data;
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};
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/* List of supported models */
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enum ksz_model {
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KSZ8563,
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KSZ8795,
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KSZ8794,
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KSZ8765,
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KSZ8830,
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KSZ9477,
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KSZ9896,
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KSZ9897,
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KSZ9893,
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KSZ9563,
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KSZ9567,
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LAN9370,
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LAN9371,
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LAN9372,
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LAN9373,
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LAN9374,
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};
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enum ksz_chip_id {
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KSZ8563_CHIP_ID = 0x8563,
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KSZ8795_CHIP_ID = 0x8795,
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KSZ8794_CHIP_ID = 0x8794,
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KSZ8765_CHIP_ID = 0x8765,
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KSZ8830_CHIP_ID = 0x8830,
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KSZ9477_CHIP_ID = 0x00947700,
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KSZ9896_CHIP_ID = 0x00989600,
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KSZ9897_CHIP_ID = 0x00989700,
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KSZ9893_CHIP_ID = 0x00989300,
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KSZ9563_CHIP_ID = 0x00956300,
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KSZ9567_CHIP_ID = 0x00956700,
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LAN9370_CHIP_ID = 0x00937000,
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LAN9371_CHIP_ID = 0x00937100,
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LAN9372_CHIP_ID = 0x00937200,
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LAN9373_CHIP_ID = 0x00937300,
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LAN9374_CHIP_ID = 0x00937400,
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};
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enum ksz_regs {
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REG_IND_CTRL_0,
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REG_IND_DATA_8,
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REG_IND_DATA_CHECK,
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REG_IND_DATA_HI,
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REG_IND_DATA_LO,
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REG_IND_MIB_CHECK,
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REG_IND_BYTE,
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P_FORCE_CTRL,
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P_LINK_STATUS,
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P_LOCAL_CTRL,
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P_NEG_RESTART_CTRL,
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P_REMOTE_STATUS,
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P_SPEED_STATUS,
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S_TAIL_TAG_CTRL,
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P_STP_CTRL,
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S_START_CTRL,
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S_BROADCAST_CTRL,
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S_MULTICAST_CTRL,
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P_XMII_CTRL_0,
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P_XMII_CTRL_1,
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};
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enum ksz_masks {
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PORT_802_1P_REMAPPING,
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SW_TAIL_TAG_ENABLE,
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MIB_COUNTER_OVERFLOW,
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MIB_COUNTER_VALID,
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VLAN_TABLE_FID,
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VLAN_TABLE_MEMBERSHIP,
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VLAN_TABLE_VALID,
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STATIC_MAC_TABLE_VALID,
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STATIC_MAC_TABLE_USE_FID,
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STATIC_MAC_TABLE_FID,
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STATIC_MAC_TABLE_OVERRIDE,
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STATIC_MAC_TABLE_FWD_PORTS,
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DYNAMIC_MAC_TABLE_ENTRIES_H,
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DYNAMIC_MAC_TABLE_MAC_EMPTY,
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DYNAMIC_MAC_TABLE_NOT_READY,
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DYNAMIC_MAC_TABLE_ENTRIES,
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DYNAMIC_MAC_TABLE_FID,
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DYNAMIC_MAC_TABLE_SRC_PORT,
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DYNAMIC_MAC_TABLE_TIMESTAMP,
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ALU_STAT_WRITE,
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ALU_STAT_READ,
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P_MII_TX_FLOW_CTRL,
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P_MII_RX_FLOW_CTRL,
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};
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enum ksz_shifts {
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VLAN_TABLE_MEMBERSHIP_S,
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VLAN_TABLE,
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STATIC_MAC_FWD_PORTS,
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STATIC_MAC_FID,
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DYNAMIC_MAC_ENTRIES_H,
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DYNAMIC_MAC_ENTRIES,
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DYNAMIC_MAC_FID,
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DYNAMIC_MAC_TIMESTAMP,
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DYNAMIC_MAC_SRC_PORT,
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ALU_STAT_INDEX,
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};
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enum ksz_xmii_ctrl0 {
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P_MII_100MBIT,
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P_MII_10MBIT,
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P_MII_FULL_DUPLEX,
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P_MII_HALF_DUPLEX,
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};
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enum ksz_xmii_ctrl1 {
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P_RGMII_SEL,
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P_RMII_SEL,
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P_GMII_SEL,
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P_MII_SEL,
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P_GMII_1GBIT,
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P_GMII_NOT_1GBIT,
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};
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struct alu_struct {
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/* entry 1 */
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u8 is_static:1;
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u8 is_src_filter:1;
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u8 is_dst_filter:1;
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u8 prio_age:3;
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u32 _reserv_0_1:23;
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u8 mstp:3;
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/* entry 2 */
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u8 is_override:1;
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u8 is_use_fid:1;
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u32 _reserv_1_1:23;
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u8 port_forward:7;
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/* entry 3 & 4*/
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u32 _reserv_2_1:9;
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u8 fid:7;
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u8 mac[ETH_ALEN];
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};
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struct ksz_dev_ops {
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int (*setup)(struct dsa_switch *ds);
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void (*teardown)(struct dsa_switch *ds);
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u32 (*get_port_addr)(int port, int offset);
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void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member);
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void (*flush_dyn_mac_table)(struct ksz_device *dev, int port);
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void (*port_cleanup)(struct ksz_device *dev, int port);
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void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port);
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int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs);
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int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val);
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int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val);
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void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr,
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u64 *cnt);
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void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr,
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u64 *dropped, u64 *cnt);
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void (*r_mib_stat64)(struct ksz_device *dev, int port);
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int (*vlan_filtering)(struct ksz_device *dev, int port,
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bool flag, struct netlink_ext_ack *extack);
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int (*vlan_add)(struct ksz_device *dev, int port,
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const struct switchdev_obj_port_vlan *vlan,
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struct netlink_ext_ack *extack);
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int (*vlan_del)(struct ksz_device *dev, int port,
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const struct switchdev_obj_port_vlan *vlan);
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int (*mirror_add)(struct ksz_device *dev, int port,
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struct dsa_mall_mirror_tc_entry *mirror,
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bool ingress, struct netlink_ext_ack *extack);
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void (*mirror_del)(struct ksz_device *dev, int port,
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struct dsa_mall_mirror_tc_entry *mirror);
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int (*fdb_add)(struct ksz_device *dev, int port,
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const unsigned char *addr, u16 vid, struct dsa_db db);
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int (*fdb_del)(struct ksz_device *dev, int port,
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const unsigned char *addr, u16 vid, struct dsa_db db);
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int (*fdb_dump)(struct ksz_device *dev, int port,
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dsa_fdb_dump_cb_t *cb, void *data);
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int (*mdb_add)(struct ksz_device *dev, int port,
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const struct switchdev_obj_port_mdb *mdb,
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struct dsa_db db);
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int (*mdb_del)(struct ksz_device *dev, int port,
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const struct switchdev_obj_port_mdb *mdb,
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struct dsa_db db);
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void (*get_caps)(struct ksz_device *dev, int port,
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struct phylink_config *config);
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int (*change_mtu)(struct ksz_device *dev, int port, int mtu);
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void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
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void (*port_init_cnt)(struct ksz_device *dev, int port);
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void (*phylink_mac_config)(struct ksz_device *dev, int port,
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unsigned int mode,
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const struct phylink_link_state *state);
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void (*phylink_mac_link_up)(struct ksz_device *dev, int port,
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unsigned int mode,
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phy_interface_t interface,
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struct phy_device *phydev, int speed,
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int duplex, bool tx_pause, bool rx_pause);
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void (*setup_rgmii_delay)(struct ksz_device *dev, int port);
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|
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int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val);
|
||
|
|
void (*config_cpu_port)(struct dsa_switch *ds);
|
||
|
|
int (*enable_stp_addr)(struct ksz_device *dev);
|
||
|
|
int (*reset)(struct ksz_device *dev);
|
||
|
|
int (*init)(struct ksz_device *dev);
|
||
|
|
void (*exit)(struct ksz_device *dev);
|
||
|
|
};
|
||
|
|
|
||
|
|
struct ksz_device *ksz_switch_alloc(struct device *base, void *priv);
|
||
|
|
int ksz_switch_register(struct ksz_device *dev);
|
||
|
|
void ksz_switch_remove(struct ksz_device *dev);
|
||
|
|
|
||
|
|
void ksz_init_mib_timer(struct ksz_device *dev);
|
||
|
|
void ksz_r_mib_stats64(struct ksz_device *dev, int port);
|
||
|
|
void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port);
|
||
|
|
void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
|
||
|
|
bool ksz_get_gbit(struct ksz_device *dev, int port);
|
||
|
|
phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
|
||
|
|
extern const struct ksz_chip_data ksz_switch_chips[];
|
||
|
|
|
||
|
|
/* Common register access functions */
|
||
|
|
|
||
|
|
static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val)
|
||
|
|
{
|
||
|
|
unsigned int value;
|
||
|
|
int ret = regmap_read(dev->regmap[0], reg, &value);
|
||
|
|
|
||
|
|
if (ret)
|
||
|
|
dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg,
|
||
|
|
ERR_PTR(ret));
|
||
|
|
|
||
|
|
*val = value;
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val)
|
||
|
|
{
|
||
|
|
unsigned int value;
|
||
|
|
int ret = regmap_read(dev->regmap[1], reg, &value);
|
||
|
|
|
||
|
|
if (ret)
|
||
|
|
dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg,
|
||
|
|
ERR_PTR(ret));
|
||
|
|
|
||
|
|
*val = value;
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val)
|
||
|
|
{
|
||
|
|
unsigned int value;
|
||
|
|
int ret = regmap_read(dev->regmap[2], reg, &value);
|
||
|
|
|
||
|
|
if (ret)
|
||
|
|
dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg,
|
||
|
|
ERR_PTR(ret));
|
||
|
|
|
||
|
|
*val = value;
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val)
|
||
|
|
{
|
||
|
|
u32 value[2];
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = regmap_bulk_read(dev->regmap[2], reg, value, 2);
|
||
|
|
if (ret)
|
||
|
|
dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg,
|
||
|
|
ERR_PTR(ret));
|
||
|
|
else
|
||
|
|
*val = (u64)value[0] << 32 | value[1];
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = regmap_write(dev->regmap[0], reg, value);
|
||
|
|
if (ret)
|
||
|
|
dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg,
|
||
|
|
ERR_PTR(ret));
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = regmap_write(dev->regmap[1], reg, value);
|
||
|
|
if (ret)
|
||
|
|
dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg,
|
||
|
|
ERR_PTR(ret));
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = regmap_write(dev->regmap[2], reg, value);
|
||
|
|
if (ret)
|
||
|
|
dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg,
|
||
|
|
ERR_PTR(ret));
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask,
|
||
|
|
u16 value)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = regmap_update_bits(dev->regmap[1], reg, mask, value);
|
||
|
|
if (ret)
|
||
|
|
dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg,
|
||
|
|
ERR_PTR(ret));
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask,
|
||
|
|
u32 value)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = regmap_update_bits(dev->regmap[2], reg, mask, value);
|
||
|
|
if (ret)
|
||
|
|
dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg,
|
||
|
|
ERR_PTR(ret));
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
|
||
|
|
{
|
||
|
|
u32 val[2];
|
||
|
|
|
||
|
|
/* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
|
||
|
|
value = swab64(value);
|
||
|
|
val[0] = swab32(value & 0xffffffffULL);
|
||
|
|
val[1] = swab32(value >> 32ULL);
|
||
|
|
|
||
|
|
return regmap_bulk_write(dev->regmap[2], reg, val, 2);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val)
|
||
|
|
{
|
||
|
|
return regmap_update_bits(dev->regmap[0], offset, mask, val);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_pread8(struct ksz_device *dev, int port, int offset,
|
||
|
|
u8 *data)
|
||
|
|
{
|
||
|
|
return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_pread16(struct ksz_device *dev, int port, int offset,
|
||
|
|
u16 *data)
|
||
|
|
{
|
||
|
|
return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_pread32(struct ksz_device *dev, int port, int offset,
|
||
|
|
u32 *data)
|
||
|
|
{
|
||
|
|
return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset,
|
||
|
|
u8 data)
|
||
|
|
{
|
||
|
|
return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset,
|
||
|
|
u16 data)
|
||
|
|
{
|
||
|
|
return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset),
|
||
|
|
data);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset,
|
||
|
|
u32 data)
|
||
|
|
{
|
||
|
|
return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset),
|
||
|
|
data);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset,
|
||
|
|
u8 mask, u8 val)
|
||
|
|
{
|
||
|
|
regmap_update_bits(dev->regmap[0],
|
||
|
|
dev->dev_ops->get_port_addr(port, offset),
|
||
|
|
mask, val);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void ksz_regmap_lock(void *__mtx)
|
||
|
|
{
|
||
|
|
struct mutex *mtx = __mtx;
|
||
|
|
mutex_lock(mtx);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void ksz_regmap_unlock(void *__mtx)
|
||
|
|
{
|
||
|
|
struct mutex *mtx = __mtx;
|
||
|
|
mutex_unlock(mtx);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
|
||
|
|
{
|
||
|
|
return dev->chip_id == KSZ8830_CHIP_ID;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int is_lan937x(struct ksz_device *dev)
|
||
|
|
{
|
||
|
|
return dev->chip_id == LAN9370_CHIP_ID ||
|
||
|
|
dev->chip_id == LAN9371_CHIP_ID ||
|
||
|
|
dev->chip_id == LAN9372_CHIP_ID ||
|
||
|
|
dev->chip_id == LAN9373_CHIP_ID ||
|
||
|
|
dev->chip_id == LAN9374_CHIP_ID;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* STP State Defines */
|
||
|
|
#define PORT_TX_ENABLE BIT(2)
|
||
|
|
#define PORT_RX_ENABLE BIT(1)
|
||
|
|
#define PORT_LEARN_DISABLE BIT(0)
|
||
|
|
|
||
|
|
/* Switch ID Defines */
|
||
|
|
#define REG_CHIP_ID0 0x00
|
||
|
|
|
||
|
|
#define SW_FAMILY_ID_M GENMASK(15, 8)
|
||
|
|
#define KSZ87_FAMILY_ID 0x87
|
||
|
|
#define KSZ88_FAMILY_ID 0x88
|
||
|
|
|
||
|
|
#define KSZ8_PORT_STATUS_0 0x08
|
||
|
|
#define KSZ8_PORT_FIBER_MODE BIT(7)
|
||
|
|
|
||
|
|
#define SW_CHIP_ID_M GENMASK(7, 4)
|
||
|
|
#define KSZ87_CHIP_ID_94 0x6
|
||
|
|
#define KSZ87_CHIP_ID_95 0x9
|
||
|
|
#define KSZ88_CHIP_ID_63 0x3
|
||
|
|
|
||
|
|
#define SW_REV_ID_M GENMASK(7, 4)
|
||
|
|
|
||
|
|
/* KSZ9893, KSZ9563, KSZ8563 specific register */
|
||
|
|
#define REG_CHIP_ID4 0x0f
|
||
|
|
#define SKU_ID_KSZ8563 0x3c
|
||
|
|
#define SKU_ID_KSZ9563 0x1c
|
||
|
|
|
||
|
|
/* Driver set switch broadcast storm protection at 10% rate. */
|
||
|
|
#define BROADCAST_STORM_PROT_RATE 10
|
||
|
|
|
||
|
|
/* 148,800 frames * 67 ms / 100 */
|
||
|
|
#define BROADCAST_STORM_VALUE 9969
|
||
|
|
|
||
|
|
#define BROADCAST_STORM_RATE_HI 0x07
|
||
|
|
#define BROADCAST_STORM_RATE_LO 0xFF
|
||
|
|
#define BROADCAST_STORM_RATE 0x07FF
|
||
|
|
|
||
|
|
#define MULTICAST_STORM_DISABLE BIT(6)
|
||
|
|
|
||
|
|
#define SW_START 0x01
|
||
|
|
|
||
|
|
/* xMII configuration */
|
||
|
|
#define P_MII_DUPLEX_M BIT(6)
|
||
|
|
#define P_MII_100MBIT_M BIT(4)
|
||
|
|
|
||
|
|
#define P_GMII_1GBIT_M BIT(6)
|
||
|
|
#define P_RGMII_ID_IG_ENABLE BIT(4)
|
||
|
|
#define P_RGMII_ID_EG_ENABLE BIT(3)
|
||
|
|
#define P_MII_MAC_MODE BIT(2)
|
||
|
|
#define P_MII_SEL_M 0x3
|
||
|
|
|
||
|
|
/* Interrupt */
|
||
|
|
#define REG_SW_PORT_INT_STATUS__1 0x001B
|
||
|
|
#define REG_SW_PORT_INT_MASK__1 0x001F
|
||
|
|
|
||
|
|
#define REG_PORT_INT_STATUS 0x001B
|
||
|
|
#define REG_PORT_INT_MASK 0x001F
|
||
|
|
|
||
|
|
#define PORT_SRC_PHY_INT 1
|
||
|
|
#define PORT_SRC_PTP_INT 2
|
||
|
|
|
||
|
|
#define KSZ8795_HUGE_PACKET_SIZE 2000
|
||
|
|
#define KSZ8863_HUGE_PACKET_SIZE 1916
|
||
|
|
#define KSZ8863_NORMAL_PACKET_SIZE 1536
|
||
|
|
#define KSZ8_LEGAL_PACKET_SIZE 1518
|
||
|
|
#define KSZ9477_MAX_FRAME_SIZE 9000
|
||
|
|
|
||
|
|
/* CBS related registers */
|
||
|
|
#define REG_PORT_MTI_QUEUE_INDEX__4 0x0900
|
||
|
|
|
||
|
|
#define REG_PORT_MTI_QUEUE_CTRL_0 0x0914
|
||
|
|
|
||
|
|
#define MTI_SCHEDULE_MODE_M 0x3
|
||
|
|
#define MTI_SCHEDULE_MODE_S 6
|
||
|
|
#define MTI_SCHEDULE_STRICT_PRIO 0
|
||
|
|
#define MTI_SCHEDULE_WRR 2
|
||
|
|
#define MTI_SHAPING_M 0x3
|
||
|
|
#define MTI_SHAPING_S 4
|
||
|
|
#define MTI_SHAPING_OFF 0
|
||
|
|
#define MTI_SHAPING_SRP 1
|
||
|
|
#define MTI_SHAPING_TIME_AWARE 2
|
||
|
|
|
||
|
|
#define REG_PORT_MTI_HI_WATER_MARK 0x0916
|
||
|
|
#define REG_PORT_MTI_LO_WATER_MARK 0x0918
|
||
|
|
|
||
|
|
/* Regmap tables generation */
|
||
|
|
#define KSZ_SPI_OP_RD 3
|
||
|
|
#define KSZ_SPI_OP_WR 2
|
||
|
|
|
||
|
|
#define swabnot_used(x) 0
|
||
|
|
|
||
|
|
#define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \
|
||
|
|
swab##swp((opcode) << ((regbits) + (regpad)))
|
||
|
|
|
||
|
|
#define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \
|
||
|
|
{ \
|
||
|
|
.name = #width, \
|
||
|
|
.val_bits = (width), \
|
||
|
|
.reg_stride = 1, \
|
||
|
|
.reg_bits = (regbits) + (regalign), \
|
||
|
|
.pad_bits = (regpad), \
|
||
|
|
.max_register = BIT(regbits) - 1, \
|
||
|
|
.cache_type = REGCACHE_NONE, \
|
||
|
|
.read_flag_mask = \
|
||
|
|
KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \
|
||
|
|
regbits, regpad), \
|
||
|
|
.write_flag_mask = \
|
||
|
|
KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \
|
||
|
|
regbits, regpad), \
|
||
|
|
.lock = ksz_regmap_lock, \
|
||
|
|
.unlock = ksz_regmap_unlock, \
|
||
|
|
.reg_format_endian = REGMAP_ENDIAN_BIG, \
|
||
|
|
.val_format_endian = REGMAP_ENDIAN_BIG \
|
||
|
|
}
|
||
|
|
|
||
|
|
#define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \
|
||
|
|
static const struct regmap_config ksz##_regmap_config[] = { \
|
||
|
|
KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \
|
||
|
|
KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \
|
||
|
|
KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|