423 lines
12 KiB
C
423 lines
12 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
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* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
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*/
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#ifndef _SJA1105_H
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#define _SJA1105_H
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#include <linux/ptp_clock_kernel.h>
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#include <linux/timecounter.h>
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#include <linux/dsa/sja1105.h>
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#include <linux/dsa/8021q.h>
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#include <net/dsa.h>
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#include <linux/mutex.h>
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#include "sja1105_static_config.h"
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#define SJA1105ET_FDB_BIN_SIZE 4
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/* The hardware value is in multiples of 10 ms.
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* The passed parameter is in multiples of 1 ms.
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*/
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#define SJA1105_AGEING_TIME_MS(ms) ((ms) / 10)
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#define SJA1105_NUM_L2_POLICERS SJA1110_MAX_L2_POLICING_COUNT
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/* Calculated assuming 1Gbps, where the clock has 125 MHz (8 ns period)
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* To avoid floating point operations, we'll multiply the degrees by 10
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* to get a "phase" and get 1 decimal point precision.
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*/
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#define SJA1105_RGMII_DELAY_PS_TO_PHASE(ps) \
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(((ps) * 360) / 800)
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#define SJA1105_RGMII_DELAY_PHASE_TO_PS(phase) \
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((800 * (phase)) / 360)
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#define SJA1105_RGMII_DELAY_PHASE_TO_HW(phase) \
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(((phase) - 738) / 9)
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#define SJA1105_RGMII_DELAY_PS_TO_HW(ps) \
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SJA1105_RGMII_DELAY_PHASE_TO_HW(SJA1105_RGMII_DELAY_PS_TO_PHASE(ps))
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/* Valid range in degrees is a value between 73.8 and 101.7
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* in 0.9 degree increments
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*/
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#define SJA1105_RGMII_DELAY_MIN_PS \
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SJA1105_RGMII_DELAY_PHASE_TO_PS(738)
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#define SJA1105_RGMII_DELAY_MAX_PS \
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SJA1105_RGMII_DELAY_PHASE_TO_PS(1017)
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typedef enum {
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SPI_READ = 0,
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SPI_WRITE = 1,
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} sja1105_spi_rw_mode_t;
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#include "sja1105_tas.h"
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#include "sja1105_ptp.h"
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enum sja1105_stats_area {
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MAC,
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HL1,
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HL2,
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ETHER,
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__MAX_SJA1105_STATS_AREA,
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};
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/* Keeps the different addresses between E/T and P/Q/R/S */
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struct sja1105_regs {
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u64 device_id;
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u64 prod_id;
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u64 status;
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u64 port_control;
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u64 rgu;
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u64 vl_status;
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u64 config;
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u64 rmii_pll1;
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u64 ptppinst;
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u64 ptppindur;
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u64 ptp_control;
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u64 ptpclkval;
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u64 ptpclkrate;
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u64 ptpclkcorp;
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u64 ptpsyncts;
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u64 ptpschtm;
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u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS];
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u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS];
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u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS];
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u64 pad_mii_id[SJA1105_MAX_NUM_PORTS];
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u64 cgu_idiv[SJA1105_MAX_NUM_PORTS];
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u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS];
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u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS];
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u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
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u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS];
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u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS];
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u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS];
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u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
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u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS];
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u64 mdio_100base_tx;
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u64 mdio_100base_t1;
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u64 pcs_base[SJA1105_MAX_NUM_PORTS];
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};
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struct sja1105_mdio_private {
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struct sja1105_private *priv;
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};
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enum {
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SJA1105_SPEED_AUTO,
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SJA1105_SPEED_10MBPS,
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SJA1105_SPEED_100MBPS,
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SJA1105_SPEED_1000MBPS,
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SJA1105_SPEED_2500MBPS,
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SJA1105_SPEED_MAX,
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};
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enum sja1105_internal_phy_t {
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SJA1105_NO_PHY = 0,
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SJA1105_PHY_BASE_TX,
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SJA1105_PHY_BASE_T1,
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};
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struct sja1105_info {
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u64 device_id;
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/* Needed for distinction between P and R, and between Q and S
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* (since the parts with/without SGMII share the same
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* switch core and device_id)
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*/
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u64 part_no;
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/* E/T and P/Q/R/S have partial timestamps of different sizes.
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* They must be reconstructed on both families anyway to get the full
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* 64-bit values back.
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*/
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int ptp_ts_bits;
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/* Also SPI commands are of different sizes to retrieve
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* the egress timestamps.
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*/
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int ptpegr_ts_bytes;
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int num_cbs_shapers;
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int max_frame_mem;
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int num_ports;
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bool multiple_cascade_ports;
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enum dsa_tag_protocol tag_proto;
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const struct sja1105_dynamic_table_ops *dyn_ops;
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const struct sja1105_table_ops *static_ops;
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const struct sja1105_regs *regs;
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bool can_limit_mcast_flood;
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int (*reset_cmd)(struct dsa_switch *ds);
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int (*setup_rgmii_delay)(const void *ctx, int port);
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/* Prototypes from include/net/dsa.h */
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int (*fdb_add_cmd)(struct dsa_switch *ds, int port,
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const unsigned char *addr, u16 vid);
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int (*fdb_del_cmd)(struct dsa_switch *ds, int port,
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const unsigned char *addr, u16 vid);
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void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd,
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enum packing_op op);
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bool (*rxtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
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void (*txtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
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int (*clocking_setup)(struct sja1105_private *priv);
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int (*pcs_mdio_read_c45)(struct mii_bus *bus, int phy, int mmd,
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int reg);
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int (*pcs_mdio_write_c45)(struct mii_bus *bus, int phy, int mmd,
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int reg, u16 val);
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int (*disable_microcontroller)(struct sja1105_private *priv);
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const char *name;
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bool supports_mii[SJA1105_MAX_NUM_PORTS];
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bool supports_rmii[SJA1105_MAX_NUM_PORTS];
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bool supports_rgmii[SJA1105_MAX_NUM_PORTS];
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bool supports_sgmii[SJA1105_MAX_NUM_PORTS];
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bool supports_2500basex[SJA1105_MAX_NUM_PORTS];
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enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS];
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const u64 port_speed[SJA1105_SPEED_MAX];
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};
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enum sja1105_key_type {
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SJA1105_KEY_BCAST,
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SJA1105_KEY_TC,
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SJA1105_KEY_VLAN_UNAWARE_VL,
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SJA1105_KEY_VLAN_AWARE_VL,
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};
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struct sja1105_key {
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enum sja1105_key_type type;
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union {
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/* SJA1105_KEY_TC */
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struct {
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int pcp;
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} tc;
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/* SJA1105_KEY_VLAN_UNAWARE_VL */
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/* SJA1105_KEY_VLAN_AWARE_VL */
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struct {
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u64 dmac;
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u16 vid;
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u16 pcp;
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} vl;
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};
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};
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enum sja1105_rule_type {
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SJA1105_RULE_BCAST_POLICER,
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SJA1105_RULE_TC_POLICER,
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SJA1105_RULE_VL,
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};
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enum sja1105_vl_type {
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SJA1105_VL_NONCRITICAL,
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SJA1105_VL_RATE_CONSTRAINED,
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SJA1105_VL_TIME_TRIGGERED,
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};
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struct sja1105_rule {
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struct list_head list;
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unsigned long cookie;
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unsigned long port_mask;
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struct sja1105_key key;
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enum sja1105_rule_type type;
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/* Action */
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union {
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/* SJA1105_RULE_BCAST_POLICER */
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struct {
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int sharindx;
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} bcast_pol;
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/* SJA1105_RULE_TC_POLICER */
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struct {
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int sharindx;
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} tc_pol;
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/* SJA1105_RULE_VL */
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struct {
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enum sja1105_vl_type type;
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unsigned long destports;
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int sharindx;
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int maxlen;
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int ipv;
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u64 base_time;
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u64 cycle_time;
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int num_entries;
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struct action_gate_entry *entries;
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struct flow_stats stats;
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} vl;
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};
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};
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struct sja1105_flow_block {
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struct list_head rules;
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bool l2_policer_used[SJA1105_NUM_L2_POLICERS];
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int num_virtual_links;
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};
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struct sja1105_private {
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struct sja1105_static_config static_config;
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int rgmii_rx_delay_ps[SJA1105_MAX_NUM_PORTS];
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int rgmii_tx_delay_ps[SJA1105_MAX_NUM_PORTS];
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phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS];
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bool fixed_link[SJA1105_MAX_NUM_PORTS];
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unsigned long ucast_egress_floods;
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unsigned long bcast_egress_floods;
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unsigned long hwts_tx_en;
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const struct sja1105_info *info;
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size_t max_xfer_len;
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struct spi_device *spidev;
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struct dsa_switch *ds;
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u16 bridge_pvid[SJA1105_MAX_NUM_PORTS];
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u16 tag_8021q_pvid[SJA1105_MAX_NUM_PORTS];
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struct sja1105_flow_block flow_block;
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/* Serializes transmission of management frames so that
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* the switch doesn't confuse them with one another.
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*/
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struct mutex mgmt_lock;
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/* PTP two-step TX timestamp ID, and its serialization lock */
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spinlock_t ts_id_lock;
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u8 ts_id;
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/* Serializes access to the dynamic config interface */
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struct mutex dynamic_config_lock;
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struct devlink_region **regions;
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struct sja1105_cbs_entry *cbs;
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struct mii_bus *mdio_base_t1;
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struct mii_bus *mdio_base_tx;
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struct mii_bus *mdio_pcs;
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struct dw_xpcs *xpcs[SJA1105_MAX_NUM_PORTS];
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struct sja1105_ptp_data ptp_data;
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struct sja1105_tas_data tas_data;
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};
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#include "sja1105_dynamic_config.h"
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struct sja1105_spi_message {
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u64 access;
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u64 read_count;
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u64 address;
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};
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/* From sja1105_main.c */
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enum sja1105_reset_reason {
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SJA1105_VLAN_FILTERING = 0,
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SJA1105_RX_HWTSTAMPING,
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SJA1105_AGEING_TIME,
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SJA1105_SCHEDULING,
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SJA1105_BEST_EFFORT_POLICING,
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SJA1105_VIRTUAL_LINKS,
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};
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int sja1105_static_config_reload(struct sja1105_private *priv,
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enum sja1105_reset_reason reason);
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int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
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struct netlink_ext_ack *extack);
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void sja1105_frame_memory_partitioning(struct sja1105_private *priv);
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/* From sja1105_mdio.c */
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int sja1105_mdiobus_register(struct dsa_switch *ds);
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void sja1105_mdiobus_unregister(struct dsa_switch *ds);
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int sja1105_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg);
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int sja1105_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, int reg,
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u16 val);
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int sja1110_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg);
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int sja1110_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, int reg,
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u16 val);
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/* From sja1105_devlink.c */
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int sja1105_devlink_setup(struct dsa_switch *ds);
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void sja1105_devlink_teardown(struct dsa_switch *ds);
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int sja1105_devlink_info_get(struct dsa_switch *ds,
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struct devlink_info_req *req,
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struct netlink_ext_ack *extack);
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/* From sja1105_spi.c */
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int sja1105_xfer_buf(const struct sja1105_private *priv,
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sja1105_spi_rw_mode_t rw, u64 reg_addr,
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u8 *buf, size_t len);
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int sja1105_xfer_u32(const struct sja1105_private *priv,
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sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value,
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struct ptp_system_timestamp *ptp_sts);
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int sja1105_xfer_u64(const struct sja1105_private *priv,
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sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value,
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struct ptp_system_timestamp *ptp_sts);
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int static_config_buf_prepare_for_upload(struct sja1105_private *priv,
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void *config_buf, int buf_len);
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int sja1105_static_config_upload(struct sja1105_private *priv);
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int sja1105_inhibit_tx(const struct sja1105_private *priv,
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unsigned long port_bitmap, bool tx_inhibited);
|
||
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extern const struct sja1105_info sja1105e_info;
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extern const struct sja1105_info sja1105t_info;
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extern const struct sja1105_info sja1105p_info;
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extern const struct sja1105_info sja1105q_info;
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extern const struct sja1105_info sja1105r_info;
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||
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|
extern const struct sja1105_info sja1105s_info;
|
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extern const struct sja1105_info sja1110a_info;
|
||
|
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extern const struct sja1105_info sja1110b_info;
|
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extern const struct sja1105_info sja1110c_info;
|
||
|
|
extern const struct sja1105_info sja1110d_info;
|
||
|
|
|
||
|
|
/* From sja1105_clocking.c */
|
||
|
|
|
||
|
|
typedef enum {
|
||
|
|
XMII_MAC = 0,
|
||
|
|
XMII_PHY = 1,
|
||
|
|
} sja1105_mii_role_t;
|
||
|
|
|
||
|
|
typedef enum {
|
||
|
|
XMII_MODE_MII = 0,
|
||
|
|
XMII_MODE_RMII = 1,
|
||
|
|
XMII_MODE_RGMII = 2,
|
||
|
|
XMII_MODE_SGMII = 3,
|
||
|
|
} sja1105_phy_interface_t;
|
||
|
|
|
||
|
|
int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port);
|
||
|
|
int sja1110_setup_rgmii_delay(const void *ctx, int port);
|
||
|
|
int sja1105_clocking_setup_port(struct sja1105_private *priv, int port);
|
||
|
|
int sja1105_clocking_setup(struct sja1105_private *priv);
|
||
|
|
int sja1110_disable_microcontroller(struct sja1105_private *priv);
|
||
|
|
|
||
|
|
/* From sja1105_ethtool.c */
|
||
|
|
void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data);
|
||
|
|
void sja1105_get_strings(struct dsa_switch *ds, int port,
|
||
|
|
u32 stringset, u8 *data);
|
||
|
|
int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset);
|
||
|
|
|
||
|
|
/* From sja1105_dynamic_config.c */
|
||
|
|
int sja1105_dynamic_config_read(struct sja1105_private *priv,
|
||
|
|
enum sja1105_blk_idx blk_idx,
|
||
|
|
int index, void *entry);
|
||
|
|
int sja1105_dynamic_config_write(struct sja1105_private *priv,
|
||
|
|
enum sja1105_blk_idx blk_idx,
|
||
|
|
int index, void *entry, bool keep);
|
||
|
|
|
||
|
|
enum sja1105_iotag {
|
||
|
|
SJA1105_C_TAG = 0, /* Inner VLAN header */
|
||
|
|
SJA1105_S_TAG = 1, /* Outer VLAN header */
|
||
|
|
};
|
||
|
|
|
||
|
|
enum sja1110_vlan_type {
|
||
|
|
SJA1110_VLAN_INVALID = 0,
|
||
|
|
SJA1110_VLAN_C_TAG = 1, /* Single inner VLAN tag */
|
||
|
|
SJA1110_VLAN_S_TAG = 2, /* Single outer VLAN tag */
|
||
|
|
SJA1110_VLAN_D_TAG = 3, /* Double tagged, use outer tag for lookup */
|
||
|
|
};
|
||
|
|
|
||
|
|
enum sja1110_shaper_type {
|
||
|
|
SJA1110_LEAKY_BUCKET_SHAPER = 0,
|
||
|
|
SJA1110_CBS_SHAPER = 1,
|
||
|
|
};
|
||
|
|
|
||
|
|
u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid);
|
||
|
|
int sja1105et_fdb_add(struct dsa_switch *ds, int port,
|
||
|
|
const unsigned char *addr, u16 vid);
|
||
|
|
int sja1105et_fdb_del(struct dsa_switch *ds, int port,
|
||
|
|
const unsigned char *addr, u16 vid);
|
||
|
|
int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
|
||
|
|
const unsigned char *addr, u16 vid);
|
||
|
|
int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
|
||
|
|
const unsigned char *addr, u16 vid);
|
||
|
|
|
||
|
|
/* From sja1105_flower.c */
|
||
|
|
int sja1105_cls_flower_del(struct dsa_switch *ds, int port,
|
||
|
|
struct flow_cls_offload *cls, bool ingress);
|
||
|
|
int sja1105_cls_flower_add(struct dsa_switch *ds, int port,
|
||
|
|
struct flow_cls_offload *cls, bool ingress);
|
||
|
|
int sja1105_cls_flower_stats(struct dsa_switch *ds, int port,
|
||
|
|
struct flow_cls_offload *cls, bool ingress);
|
||
|
|
void sja1105_flower_setup(struct dsa_switch *ds);
|
||
|
|
void sja1105_flower_teardown(struct dsa_switch *ds);
|
||
|
|
struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv,
|
||
|
|
unsigned long cookie);
|
||
|
|
|
||
|
|
#endif
|