281 lines
12 KiB
C
281 lines
12 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Actions Semi Owl SoCs Ethernet MAC driver
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*
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* Copyright (c) 2012 Actions Semi Inc.
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* Copyright (c) 2021 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
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*/
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#ifndef __OWL_EMAC_H__
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#define __OWL_EMAC_H__
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#define OWL_EMAC_DRVNAME "owl-emac"
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#define OWL_EMAC_POLL_DELAY_USEC 5
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#define OWL_EMAC_MDIO_POLL_TIMEOUT_USEC 1000
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#define OWL_EMAC_RESET_POLL_TIMEOUT_USEC 2000
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#define OWL_EMAC_TX_TIMEOUT (2 * HZ)
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#define OWL_EMAC_MTU_MIN ETH_MIN_MTU
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#define OWL_EMAC_MTU_MAX ETH_DATA_LEN
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#define OWL_EMAC_RX_FRAME_MAX_LEN (ETH_FRAME_LEN + ETH_FCS_LEN)
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#define OWL_EMAC_SKB_ALIGN 4
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#define OWL_EMAC_SKB_RESERVE 18
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#define OWL_EMAC_MAX_MULTICAST_ADDRS 14
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#define OWL_EMAC_SETUP_FRAME_LEN 192
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#define OWL_EMAC_RX_RING_SIZE 64
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#define OWL_EMAC_TX_RING_SIZE 32
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/* Bus mode register */
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#define OWL_EMAC_REG_MAC_CSR0 0x0000
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#define OWL_EMAC_BIT_MAC_CSR0_SWR BIT(0) /* Software reset */
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/* Transmit/receive poll demand registers */
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#define OWL_EMAC_REG_MAC_CSR1 0x0008
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#define OWL_EMAC_VAL_MAC_CSR1_TPD 0x01
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#define OWL_EMAC_REG_MAC_CSR2 0x0010
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#define OWL_EMAC_VAL_MAC_CSR2_RPD 0x01
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/* Receive/transmit descriptor list base address registers */
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#define OWL_EMAC_REG_MAC_CSR3 0x0018
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#define OWL_EMAC_REG_MAC_CSR4 0x0020
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/* Status register */
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#define OWL_EMAC_REG_MAC_CSR5 0x0028
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#define OWL_EMAC_MSK_MAC_CSR5_TS GENMASK(22, 20) /* Transmit process state */
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#define OWL_EMAC_OFF_MAC_CSR5_TS 20
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#define OWL_EMAC_VAL_MAC_CSR5_TS_DATA 0x03 /* Transferring data HOST -> FIFO */
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#define OWL_EMAC_VAL_MAC_CSR5_TS_CDES 0x07 /* Closing transmit descriptor */
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#define OWL_EMAC_MSK_MAC_CSR5_RS GENMASK(19, 17) /* Receive process state */
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#define OWL_EMAC_OFF_MAC_CSR5_RS 17
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#define OWL_EMAC_VAL_MAC_CSR5_RS_FDES 0x01 /* Fetching receive descriptor */
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#define OWL_EMAC_VAL_MAC_CSR5_RS_CDES 0x05 /* Closing receive descriptor */
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#define OWL_EMAC_VAL_MAC_CSR5_RS_DATA 0x07 /* Transferring data FIFO -> HOST */
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#define OWL_EMAC_BIT_MAC_CSR5_NIS BIT(16) /* Normal interrupt summary */
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#define OWL_EMAC_BIT_MAC_CSR5_AIS BIT(15) /* Abnormal interrupt summary */
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#define OWL_EMAC_BIT_MAC_CSR5_ERI BIT(14) /* Early receive interrupt */
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#define OWL_EMAC_BIT_MAC_CSR5_GTE BIT(11) /* General-purpose timer expiration */
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#define OWL_EMAC_BIT_MAC_CSR5_ETI BIT(10) /* Early transmit interrupt */
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#define OWL_EMAC_BIT_MAC_CSR5_RPS BIT(8) /* Receive process stopped */
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#define OWL_EMAC_BIT_MAC_CSR5_RU BIT(7) /* Receive buffer unavailable */
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#define OWL_EMAC_BIT_MAC_CSR5_RI BIT(6) /* Receive interrupt */
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#define OWL_EMAC_BIT_MAC_CSR5_UNF BIT(5) /* Transmit underflow */
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#define OWL_EMAC_BIT_MAC_CSR5_LCIS BIT(4) /* Link change status */
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#define OWL_EMAC_BIT_MAC_CSR5_LCIQ BIT(3) /* Link change interrupt */
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#define OWL_EMAC_BIT_MAC_CSR5_TU BIT(2) /* Transmit buffer unavailable */
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#define OWL_EMAC_BIT_MAC_CSR5_TPS BIT(1) /* Transmit process stopped */
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#define OWL_EMAC_BIT_MAC_CSR5_TI BIT(0) /* Transmit interrupt */
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/* Operation mode register */
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#define OWL_EMAC_REG_MAC_CSR6 0x0030
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#define OWL_EMAC_BIT_MAC_CSR6_RA BIT(30) /* Receive all */
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#define OWL_EMAC_BIT_MAC_CSR6_TTM BIT(22) /* Transmit threshold mode */
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#define OWL_EMAC_BIT_MAC_CSR6_SF BIT(21) /* Store and forward */
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#define OWL_EMAC_MSK_MAC_CSR6_SPEED GENMASK(17, 16) /* Eth speed selection */
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#define OWL_EMAC_OFF_MAC_CSR6_SPEED 16
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#define OWL_EMAC_VAL_MAC_CSR6_SPEED_100M 0x00
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#define OWL_EMAC_VAL_MAC_CSR6_SPEED_10M 0x02
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#define OWL_EMAC_BIT_MAC_CSR6_ST BIT(13) /* Start/stop transmit command */
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#define OWL_EMAC_BIT_MAC_CSR6_LP BIT(10) /* Loopback mode */
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#define OWL_EMAC_BIT_MAC_CSR6_FD BIT(9) /* Full duplex mode */
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#define OWL_EMAC_BIT_MAC_CSR6_PM BIT(7) /* Pass all multicast */
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#define OWL_EMAC_BIT_MAC_CSR6_PR BIT(6) /* Promiscuous mode */
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#define OWL_EMAC_BIT_MAC_CSR6_IF BIT(4) /* Inverse filtering */
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#define OWL_EMAC_BIT_MAC_CSR6_PB BIT(3) /* Pass bad frames */
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#define OWL_EMAC_BIT_MAC_CSR6_HO BIT(2) /* Hash only filtering mode */
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#define OWL_EMAC_BIT_MAC_CSR6_SR BIT(1) /* Start/stop receive command */
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#define OWL_EMAC_BIT_MAC_CSR6_HP BIT(0) /* Hash/perfect receive filtering mode */
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#define OWL_EMAC_MSK_MAC_CSR6_STSR (OWL_EMAC_BIT_MAC_CSR6_ST | \
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OWL_EMAC_BIT_MAC_CSR6_SR)
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/* Interrupt enable register */
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#define OWL_EMAC_REG_MAC_CSR7 0x0038
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#define OWL_EMAC_BIT_MAC_CSR7_NIE BIT(16) /* Normal interrupt summary enable */
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#define OWL_EMAC_BIT_MAC_CSR7_AIE BIT(15) /* Abnormal interrupt summary enable */
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#define OWL_EMAC_BIT_MAC_CSR7_ERE BIT(14) /* Early receive interrupt enable */
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#define OWL_EMAC_BIT_MAC_CSR7_GTE BIT(11) /* General-purpose timer overflow */
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#define OWL_EMAC_BIT_MAC_CSR7_ETE BIT(10) /* Early transmit interrupt enable */
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#define OWL_EMAC_BIT_MAC_CSR7_RSE BIT(8) /* Receive stopped enable */
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#define OWL_EMAC_BIT_MAC_CSR7_RUE BIT(7) /* Receive buffer unavailable enable */
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#define OWL_EMAC_BIT_MAC_CSR7_RIE BIT(6) /* Receive interrupt enable */
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#define OWL_EMAC_BIT_MAC_CSR7_UNE BIT(5) /* Underflow interrupt enable */
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#define OWL_EMAC_BIT_MAC_CSR7_TUE BIT(2) /* Transmit buffer unavailable enable */
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#define OWL_EMAC_BIT_MAC_CSR7_TSE BIT(1) /* Transmit stopped enable */
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#define OWL_EMAC_BIT_MAC_CSR7_TIE BIT(0) /* Transmit interrupt enable */
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#define OWL_EMAC_BIT_MAC_CSR7_ALL_NOT_TUE (OWL_EMAC_BIT_MAC_CSR7_ERE | \
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OWL_EMAC_BIT_MAC_CSR7_GTE | \
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OWL_EMAC_BIT_MAC_CSR7_ETE | \
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OWL_EMAC_BIT_MAC_CSR7_RSE | \
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OWL_EMAC_BIT_MAC_CSR7_RUE | \
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OWL_EMAC_BIT_MAC_CSR7_RIE | \
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OWL_EMAC_BIT_MAC_CSR7_UNE | \
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OWL_EMAC_BIT_MAC_CSR7_TSE | \
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OWL_EMAC_BIT_MAC_CSR7_TIE)
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/* Missed frames and overflow counter register */
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#define OWL_EMAC_REG_MAC_CSR8 0x0040
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/* MII management and serial ROM register */
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#define OWL_EMAC_REG_MAC_CSR9 0x0048
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/* MII serial management register */
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#define OWL_EMAC_REG_MAC_CSR10 0x0050
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#define OWL_EMAC_BIT_MAC_CSR10_SB BIT(31) /* Start transfer or busy */
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#define OWL_EMAC_MSK_MAC_CSR10_CLKDIV GENMASK(30, 28) /* Clock divider */
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#define OWL_EMAC_OFF_MAC_CSR10_CLKDIV 28
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#define OWL_EMAC_VAL_MAC_CSR10_CLKDIV_128 0x04
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#define OWL_EMAC_VAL_MAC_CSR10_OPCODE_WR 0x01 /* Register write command */
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#define OWL_EMAC_OFF_MAC_CSR10_OPCODE 26 /* Operation mode */
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#define OWL_EMAC_VAL_MAC_CSR10_OPCODE_DCG 0x00 /* Disable clock generation */
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#define OWL_EMAC_VAL_MAC_CSR10_OPCODE_WR 0x01 /* Register write command */
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#define OWL_EMAC_VAL_MAC_CSR10_OPCODE_RD 0x02 /* Register read command */
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#define OWL_EMAC_VAL_MAC_CSR10_OPCODE_CDS 0x03 /* Clock divider set */
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#define OWL_EMAC_MSK_MAC_CSR10_PHYADD GENMASK(25, 21) /* Physical layer address */
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#define OWL_EMAC_OFF_MAC_CSR10_PHYADD 21
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#define OWL_EMAC_MSK_MAC_CSR10_REGADD GENMASK(20, 16) /* Register address */
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#define OWL_EMAC_OFF_MAC_CSR10_REGADD 16
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#define OWL_EMAC_MSK_MAC_CSR10_DATA GENMASK(15, 0) /* Register data */
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/* General-purpose timer and interrupt mitigation control register */
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#define OWL_EMAC_REG_MAC_CSR11 0x0058
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#define OWL_EMAC_OFF_MAC_CSR11_TT 27 /* Transmit timer */
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#define OWL_EMAC_OFF_MAC_CSR11_NTP 24 /* No. of transmit packets */
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#define OWL_EMAC_OFF_MAC_CSR11_RT 20 /* Receive timer */
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#define OWL_EMAC_OFF_MAC_CSR11_NRP 17 /* No. of receive packets */
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/* MAC address low/high registers */
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#define OWL_EMAC_REG_MAC_CSR16 0x0080
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#define OWL_EMAC_REG_MAC_CSR17 0x0088
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/* Pause time & cache thresholds register */
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#define OWL_EMAC_REG_MAC_CSR18 0x0090
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#define OWL_EMAC_OFF_MAC_CSR18_CPTL 24 /* Cache pause threshold level */
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#define OWL_EMAC_OFF_MAC_CSR18_CRTL 16 /* Cache restart threshold level */
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#define OWL_EMAC_OFF_MAC_CSR18_PQT 0 /* Flow control pause quanta time */
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/* FIFO pause & restart threshold register */
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#define OWL_EMAC_REG_MAC_CSR19 0x0098
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#define OWL_EMAC_OFF_MAC_CSR19_FPTL 16 /* FIFO pause threshold level */
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#define OWL_EMAC_OFF_MAC_CSR19_FRTL 0 /* FIFO restart threshold level */
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/* Flow control setup & status register */
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#define OWL_EMAC_REG_MAC_CSR20 0x00A0
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#define OWL_EMAC_BIT_MAC_CSR20_FCE BIT(31) /* Flow Control Enable */
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#define OWL_EMAC_BIT_MAC_CSR20_TUE BIT(30) /* Transmit Un-pause frames Enable */
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#define OWL_EMAC_BIT_MAC_CSR20_TPE BIT(29) /* Transmit Pause frames Enable */
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#define OWL_EMAC_BIT_MAC_CSR20_RPE BIT(28) /* Receive Pause frames Enable */
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#define OWL_EMAC_BIT_MAC_CSR20_BPE BIT(27) /* Back pressure (half-duplex) Enable */
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/* MII control register */
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#define OWL_EMAC_REG_MAC_CTRL 0x00B0
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#define OWL_EMAC_BIT_MAC_CTRL_RRSB BIT(8) /* RMII_REFCLK select bit */
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#define OWL_EMAC_OFF_MAC_CTRL_SSDC 4 /* SMII SYNC delay cycle */
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#define OWL_EMAC_BIT_MAC_CTRL_RCPS BIT(1) /* REF_CLK phase select */
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#define OWL_EMAC_BIT_MAC_CTRL_RSIS BIT(0) /* RMII/SMII interface select */
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/* Receive descriptor status field */
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#define OWL_EMAC_BIT_RDES0_OWN BIT(31) /* Ownership bit */
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#define OWL_EMAC_BIT_RDES0_FF BIT(30) /* Filtering fail */
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#define OWL_EMAC_MSK_RDES0_FL GENMASK(29, 16) /* Frame length */
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#define OWL_EMAC_OFF_RDES0_FL 16
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#define OWL_EMAC_BIT_RDES0_ES BIT(15) /* Error summary */
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#define OWL_EMAC_BIT_RDES0_DE BIT(14) /* Descriptor error */
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#define OWL_EMAC_BIT_RDES0_RF BIT(11) /* Runt frame */
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#define OWL_EMAC_BIT_RDES0_MF BIT(10) /* Multicast frame */
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#define OWL_EMAC_BIT_RDES0_FS BIT(9) /* First descriptor */
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#define OWL_EMAC_BIT_RDES0_LS BIT(8) /* Last descriptor */
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#define OWL_EMAC_BIT_RDES0_TL BIT(7) /* Frame too long */
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#define OWL_EMAC_BIT_RDES0_CS BIT(6) /* Collision seen */
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#define OWL_EMAC_BIT_RDES0_FT BIT(5) /* Frame type */
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#define OWL_EMAC_BIT_RDES0_RE BIT(3) /* Report on MII error */
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#define OWL_EMAC_BIT_RDES0_DB BIT(2) /* Dribbling bit */
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#define OWL_EMAC_BIT_RDES0_CE BIT(1) /* CRC error */
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#define OWL_EMAC_BIT_RDES0_ZERO BIT(0) /* Legal frame length indicator */
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/* Receive descriptor control and count field */
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#define OWL_EMAC_BIT_RDES1_RER BIT(25) /* Receive end of ring */
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#define OWL_EMAC_MSK_RDES1_RBS1 GENMASK(10, 0) /* Buffer 1 size */
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/* Transmit descriptor status field */
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#define OWL_EMAC_BIT_TDES0_OWN BIT(31) /* Ownership bit */
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#define OWL_EMAC_BIT_TDES0_ES BIT(15) /* Error summary */
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#define OWL_EMAC_BIT_TDES0_LO BIT(11) /* Loss of carrier */
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#define OWL_EMAC_BIT_TDES0_NC BIT(10) /* No carrier */
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#define OWL_EMAC_BIT_TDES0_LC BIT(9) /* Late collision */
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#define OWL_EMAC_BIT_TDES0_EC BIT(8) /* Excessive collisions */
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#define OWL_EMAC_MSK_TDES0_CC GENMASK(6, 3) /* Collision count */
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#define OWL_EMAC_BIT_TDES0_UF BIT(1) /* Underflow error */
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#define OWL_EMAC_BIT_TDES0_DE BIT(0) /* Deferred */
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/* Transmit descriptor control and count field */
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#define OWL_EMAC_BIT_TDES1_IC BIT(31) /* Interrupt on completion */
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#define OWL_EMAC_BIT_TDES1_LS BIT(30) /* Last descriptor */
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#define OWL_EMAC_BIT_TDES1_FS BIT(29) /* First descriptor */
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#define OWL_EMAC_BIT_TDES1_FT1 BIT(28) /* Filtering type */
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#define OWL_EMAC_BIT_TDES1_SET BIT(27) /* Setup packet */
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#define OWL_EMAC_BIT_TDES1_AC BIT(26) /* Add CRC disable */
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#define OWL_EMAC_BIT_TDES1_TER BIT(25) /* Transmit end of ring */
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#define OWL_EMAC_BIT_TDES1_DPD BIT(23) /* Disabled padding */
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#define OWL_EMAC_BIT_TDES1_FT0 BIT(22) /* Filtering type */
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#define OWL_EMAC_MSK_TDES1_TBS1 GENMASK(10, 0) /* Buffer 1 size */
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static const char *const owl_emac_clk_names[] = { "eth", "rmii" };
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#define OWL_EMAC_NCLKS ARRAY_SIZE(owl_emac_clk_names)
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enum owl_emac_clk_map {
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OWL_EMAC_CLK_ETH = 0,
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OWL_EMAC_CLK_RMII
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};
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struct owl_emac_addr_list {
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u8 addrs[OWL_EMAC_MAX_MULTICAST_ADDRS][ETH_ALEN];
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int count;
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};
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/* TX/RX descriptors */
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struct owl_emac_ring_desc {
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u32 status;
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u32 control;
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u32 buf_addr;
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u32 reserved; /* 2nd buffer address is not used */
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};
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struct owl_emac_ring {
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struct owl_emac_ring_desc *descs;
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dma_addr_t descs_dma;
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struct sk_buff **skbs;
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dma_addr_t *skbs_dma;
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unsigned int size;
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unsigned int head;
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unsigned int tail;
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};
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struct owl_emac_priv {
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struct net_device *netdev;
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void __iomem *base;
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struct clk_bulk_data clks[OWL_EMAC_NCLKS];
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struct reset_control *reset;
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struct owl_emac_ring rx_ring;
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struct owl_emac_ring tx_ring;
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struct mii_bus *mii;
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||
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struct napi_struct napi;
|
||
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phy_interface_t phy_mode;
|
||
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unsigned int link;
|
||
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|
int speed;
|
||
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int duplex;
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||
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int pause;
|
||
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struct owl_emac_addr_list mcaddr_list;
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||
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|
||
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struct work_struct mac_reset_task;
|
||
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||
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u32 msg_enable; /* Debug message level */
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||
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spinlock_t lock; /* Sync concurrent ring access */
|
||
|
|
};
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||
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#endif /* __OWL_EMAC_H__ */
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