375 lines
11 KiB
C
375 lines
11 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Cavium, Inc.
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*/
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#ifndef NICVF_QUEUES_H
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#define NICVF_QUEUES_H
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#include <linux/netdevice.h>
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#include <linux/iommu.h>
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#include <net/xdp.h>
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#include "q_struct.h"
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#define MAX_QUEUE_SET 128
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#define MAX_RCV_QUEUES_PER_QS 8
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#define MAX_RCV_BUF_DESC_RINGS_PER_QS 2
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#define MAX_SND_QUEUES_PER_QS 8
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#define MAX_CMP_QUEUES_PER_QS 8
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/* VF's queue interrupt ranges */
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#define NICVF_INTR_ID_CQ 0
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#define NICVF_INTR_ID_SQ 8
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#define NICVF_INTR_ID_RBDR 16
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#define NICVF_INTR_ID_MISC 18
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#define NICVF_INTR_ID_QS_ERR 19
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#define for_each_cq_irq(irq) \
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for (irq = NICVF_INTR_ID_CQ; irq < NICVF_INTR_ID_SQ; irq++)
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#define for_each_sq_irq(irq) \
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for (irq = NICVF_INTR_ID_SQ; irq < NICVF_INTR_ID_RBDR; irq++)
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#define for_each_rbdr_irq(irq) \
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for (irq = NICVF_INTR_ID_RBDR; irq < NICVF_INTR_ID_MISC; irq++)
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#define RBDR_SIZE0 0ULL /* 8K entries */
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#define RBDR_SIZE1 1ULL /* 16K entries */
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#define RBDR_SIZE2 2ULL /* 32K entries */
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#define RBDR_SIZE3 3ULL /* 64K entries */
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#define RBDR_SIZE4 4ULL /* 126K entries */
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#define RBDR_SIZE5 5ULL /* 256K entries */
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#define RBDR_SIZE6 6ULL /* 512K entries */
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#define SND_QUEUE_SIZE0 0ULL /* 1K entries */
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#define SND_QUEUE_SIZE1 1ULL /* 2K entries */
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#define SND_QUEUE_SIZE2 2ULL /* 4K entries */
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#define SND_QUEUE_SIZE3 3ULL /* 8K entries */
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#define SND_QUEUE_SIZE4 4ULL /* 16K entries */
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#define SND_QUEUE_SIZE5 5ULL /* 32K entries */
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#define SND_QUEUE_SIZE6 6ULL /* 64K entries */
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#define CMP_QUEUE_SIZE0 0ULL /* 1K entries */
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#define CMP_QUEUE_SIZE1 1ULL /* 2K entries */
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#define CMP_QUEUE_SIZE2 2ULL /* 4K entries */
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#define CMP_QUEUE_SIZE3 3ULL /* 8K entries */
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#define CMP_QUEUE_SIZE4 4ULL /* 16K entries */
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#define CMP_QUEUE_SIZE5 5ULL /* 32K entries */
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#define CMP_QUEUE_SIZE6 6ULL /* 64K entries */
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/* Default queue count per QS, its lengths and threshold values */
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#define DEFAULT_RBDR_CNT 1
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#define SND_QSIZE SND_QUEUE_SIZE0
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#define SND_QUEUE_LEN (1ULL << (SND_QSIZE + 10))
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#define MIN_SND_QUEUE_LEN (1ULL << (SND_QUEUE_SIZE0 + 10))
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#define MAX_SND_QUEUE_LEN (1ULL << (SND_QUEUE_SIZE6 + 10))
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#define SND_QUEUE_THRESH 2ULL
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#define MIN_SQ_DESC_PER_PKT_XMIT 2
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/* Since timestamp not enabled, otherwise 2 */
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#define MAX_CQE_PER_PKT_XMIT 1
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/* Keep CQ and SQ sizes same, if timestamping
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* is enabled this equation will change.
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*/
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#define CMP_QSIZE CMP_QUEUE_SIZE0
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#define CMP_QUEUE_LEN (1ULL << (CMP_QSIZE + 10))
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#define MIN_CMP_QUEUE_LEN (1ULL << (CMP_QUEUE_SIZE0 + 10))
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#define MAX_CMP_QUEUE_LEN (1ULL << (CMP_QUEUE_SIZE6 + 10))
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#define CMP_QUEUE_CQE_THRESH (NAPI_POLL_WEIGHT / 2)
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#define CMP_QUEUE_TIMER_THRESH 80 /* ~2usec */
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/* No of CQEs that might anyway gets used by HW due to pipelining
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* effects irrespective of PASS/DROP/LEVELS being configured
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*/
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#define CMP_QUEUE_PIPELINE_RSVD 544
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#define RBDR_SIZE RBDR_SIZE0
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#define RCV_BUF_COUNT (1ULL << (RBDR_SIZE + 13))
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#define MAX_RCV_BUF_COUNT (1ULL << (RBDR_SIZE6 + 13))
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#define RBDR_THRESH (RCV_BUF_COUNT / 2)
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#define DMA_BUFFER_LEN 1536 /* In multiples of 128bytes */
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#define RCV_FRAG_LEN (SKB_DATA_ALIGN(DMA_BUFFER_LEN + NET_SKB_PAD) + \
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SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
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#define MAX_CQES_FOR_TX ((SND_QUEUE_LEN / MIN_SQ_DESC_PER_PKT_XMIT) * \
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MAX_CQE_PER_PKT_XMIT)
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/* RED and Backpressure levels of CQ for pkt reception
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* For CQ, level is a measure of emptiness i.e 0x0 means full
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* eg: For CQ of size 4K, and for pass/drop levels of 160/144
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* HW accepts pkt if unused CQE >= 2560
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* RED accepts pkt if unused CQE < 2304 & >= 2560
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* DROPs pkts if unused CQE < 2304
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*/
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#define RQ_PASS_CQ_LVL 224ULL
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#define RQ_DROP_CQ_LVL 216ULL
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/* RED and Backpressure levels of RBDR for pkt reception
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* For RBDR, level is a measure of fullness i.e 0x0 means empty
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* eg: For RBDR of size 8K, and for pass/drop levels of 4/0
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* HW accepts pkt if unused RBs >= 256
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* RED accepts pkt if unused RBs < 256 & >= 0
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* DROPs pkts if unused RBs < 0
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*/
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#define RQ_PASS_RBDR_LVL 8ULL
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#define RQ_DROP_RBDR_LVL 0ULL
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/* Descriptor size in bytes */
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#define SND_QUEUE_DESC_SIZE 16
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#define CMP_QUEUE_DESC_SIZE 512
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/* Buffer / descriptor alignments */
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#define NICVF_RCV_BUF_ALIGN 7
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#define NICVF_RCV_BUF_ALIGN_BYTES (1ULL << NICVF_RCV_BUF_ALIGN)
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#define NICVF_CQ_BASE_ALIGN_BYTES 512 /* 9 bits */
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#define NICVF_SQ_BASE_ALIGN_BYTES 128 /* 7 bits */
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#define NICVF_ALIGNED_ADDR(ADDR, ALIGN_BYTES) ALIGN(ADDR, ALIGN_BYTES)
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/* Queue enable/disable */
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#define NICVF_SQ_EN BIT_ULL(19)
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/* Queue reset */
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#define NICVF_CQ_RESET BIT_ULL(41)
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#define NICVF_SQ_RESET BIT_ULL(17)
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#define NICVF_RBDR_RESET BIT_ULL(43)
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enum CQ_RX_ERRLVL_E {
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CQ_ERRLVL_MAC,
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CQ_ERRLVL_L2,
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CQ_ERRLVL_L3,
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CQ_ERRLVL_L4,
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};
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enum CQ_RX_ERROP_E {
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CQ_RX_ERROP_RE_NONE = 0x0,
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CQ_RX_ERROP_RE_PARTIAL = 0x1,
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CQ_RX_ERROP_RE_JABBER = 0x2,
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CQ_RX_ERROP_RE_FCS = 0x7,
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CQ_RX_ERROP_RE_TERMINATE = 0x9,
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CQ_RX_ERROP_RE_RX_CTL = 0xb,
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CQ_RX_ERROP_PREL2_ERR = 0x1f,
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CQ_RX_ERROP_L2_FRAGMENT = 0x20,
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CQ_RX_ERROP_L2_OVERRUN = 0x21,
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CQ_RX_ERROP_L2_PFCS = 0x22,
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CQ_RX_ERROP_L2_PUNY = 0x23,
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CQ_RX_ERROP_L2_MAL = 0x24,
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CQ_RX_ERROP_L2_OVERSIZE = 0x25,
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CQ_RX_ERROP_L2_UNDERSIZE = 0x26,
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CQ_RX_ERROP_L2_LENMISM = 0x27,
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CQ_RX_ERROP_L2_PCLP = 0x28,
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CQ_RX_ERROP_IP_NOT = 0x41,
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CQ_RX_ERROP_IP_CSUM_ERR = 0x42,
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CQ_RX_ERROP_IP_MAL = 0x43,
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CQ_RX_ERROP_IP_MALD = 0x44,
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CQ_RX_ERROP_IP_HOP = 0x45,
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CQ_RX_ERROP_L3_ICRC = 0x46,
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CQ_RX_ERROP_L3_PCLP = 0x47,
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CQ_RX_ERROP_L4_MAL = 0x61,
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CQ_RX_ERROP_L4_CHK = 0x62,
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CQ_RX_ERROP_UDP_LEN = 0x63,
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CQ_RX_ERROP_L4_PORT = 0x64,
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CQ_RX_ERROP_TCP_FLAG = 0x65,
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CQ_RX_ERROP_TCP_OFFSET = 0x66,
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CQ_RX_ERROP_L4_PCLP = 0x67,
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CQ_RX_ERROP_RBDR_TRUNC = 0x70,
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};
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enum CQ_TX_ERROP_E {
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CQ_TX_ERROP_GOOD = 0x0,
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CQ_TX_ERROP_DESC_FAULT = 0x10,
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CQ_TX_ERROP_HDR_CONS_ERR = 0x11,
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CQ_TX_ERROP_SUBDC_ERR = 0x12,
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CQ_TX_ERROP_MAX_SIZE_VIOL = 0x13,
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CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80,
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CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81,
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CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82,
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CQ_TX_ERROP_LOCK_VIOL = 0x83,
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CQ_TX_ERROP_DATA_FAULT = 0x84,
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CQ_TX_ERROP_TSTMP_CONFLICT = 0x85,
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CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86,
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CQ_TX_ERROP_MEM_FAULT = 0x87,
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CQ_TX_ERROP_CK_OVERLAP = 0x88,
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CQ_TX_ERROP_CK_OFLOW = 0x89,
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CQ_TX_ERROP_ENUM_LAST = 0x8a,
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};
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enum RQ_SQ_STATS {
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RQ_SQ_STATS_OCTS,
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RQ_SQ_STATS_PKTS,
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};
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struct rx_tx_queue_stats {
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u64 bytes;
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u64 pkts;
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} ____cacheline_aligned_in_smp;
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struct q_desc_mem {
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dma_addr_t dma;
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u64 size;
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u32 q_len;
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dma_addr_t phys_base;
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void *base;
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void *unalign_base;
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};
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struct pgcache {
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struct page *page;
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int ref_count;
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u64 dma_addr;
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};
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struct rbdr {
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bool enable;
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u32 dma_size;
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u32 frag_len;
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u32 thresh; /* Threshold level for interrupt */
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void *desc;
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u32 head;
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u32 tail;
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struct q_desc_mem dmem;
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bool is_xdp;
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/* For page recycling */
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int pgidx;
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int pgcnt;
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int pgalloc;
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struct pgcache *pgcache;
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} ____cacheline_aligned_in_smp;
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struct rcv_queue {
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bool enable;
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struct rbdr *rbdr_start;
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struct rbdr *rbdr_cont;
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bool en_tcp_reassembly;
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u8 cq_qs; /* CQ's QS to which this RQ is assigned */
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u8 cq_idx; /* CQ index (0 to 7) in the QS */
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u8 cont_rbdr_qs; /* Continue buffer ptrs - QS num */
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u8 cont_qs_rbdr_idx; /* RBDR idx in the cont QS */
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u8 start_rbdr_qs; /* First buffer ptrs - QS num */
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u8 start_qs_rbdr_idx; /* RBDR idx in the above QS */
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u8 caching;
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struct rx_tx_queue_stats stats;
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struct xdp_rxq_info xdp_rxq;
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} ____cacheline_aligned_in_smp;
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struct cmp_queue {
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bool enable;
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u16 thresh;
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spinlock_t lock; /* lock to serialize processing CQEs */
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void *desc;
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struct q_desc_mem dmem;
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int irq;
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} ____cacheline_aligned_in_smp;
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struct snd_queue {
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bool enable;
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u8 cq_qs; /* CQ's QS to which this SQ is pointing */
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u8 cq_idx; /* CQ index (0 to 7) in the above QS */
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u16 thresh;
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atomic_t free_cnt;
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u32 head;
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u32 tail;
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u64 *skbuff;
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void *desc;
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u64 *xdp_page;
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u16 xdp_desc_cnt;
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u16 xdp_free_cnt;
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bool is_xdp;
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/* For TSO segment's header */
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char *tso_hdrs;
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dma_addr_t tso_hdrs_phys;
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cpumask_t affinity_mask;
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struct q_desc_mem dmem;
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struct rx_tx_queue_stats stats;
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} ____cacheline_aligned_in_smp;
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struct queue_set {
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bool enable;
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bool be_en;
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u8 vnic_id;
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u8 rq_cnt;
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u8 cq_cnt;
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u64 cq_len;
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u8 sq_cnt;
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u64 sq_len;
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u8 rbdr_cnt;
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u64 rbdr_len;
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struct rcv_queue rq[MAX_RCV_QUEUES_PER_QS];
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struct cmp_queue cq[MAX_CMP_QUEUES_PER_QS];
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struct snd_queue sq[MAX_SND_QUEUES_PER_QS];
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struct rbdr rbdr[MAX_RCV_BUF_DESC_RINGS_PER_QS];
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} ____cacheline_aligned_in_smp;
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#define GET_RBDR_DESC(RING, idx)\
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(&(((struct rbdr_entry_t *)((RING)->desc))[idx]))
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#define GET_SQ_DESC(RING, idx)\
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(&(((struct sq_hdr_subdesc *)((RING)->desc))[idx]))
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#define GET_CQ_DESC(RING, idx)\
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(&(((union cq_desc_t *)((RING)->desc))[idx]))
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/* CQ status bits */
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#define CQ_WR_FULL BIT(26)
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#define CQ_WR_DISABLE BIT(25)
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#define CQ_WR_FAULT BIT(24)
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#define CQ_CQE_COUNT (0xFFFF << 0)
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#define CQ_ERR_MASK (CQ_WR_FULL | CQ_WR_DISABLE | CQ_WR_FAULT)
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static inline u64 nicvf_iova_to_phys(struct nicvf *nic, dma_addr_t dma_addr)
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{
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/* Translation is installed only when IOMMU is present */
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if (nic->iommu_domain)
|
||
|
|
return iommu_iova_to_phys(nic->iommu_domain, dma_addr);
|
||
|
|
return dma_addr;
|
||
|
|
}
|
||
|
|
|
||
|
|
void nicvf_unmap_sndq_buffers(struct nicvf *nic, struct snd_queue *sq,
|
||
|
|
int hdr_sqe, u8 subdesc_cnt);
|
||
|
|
void nicvf_config_vlan_stripping(struct nicvf *nic,
|
||
|
|
netdev_features_t features);
|
||
|
|
int nicvf_set_qset_resources(struct nicvf *nic);
|
||
|
|
int nicvf_config_data_transfer(struct nicvf *nic, bool enable);
|
||
|
|
void nicvf_qset_config(struct nicvf *nic, bool enable);
|
||
|
|
void nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs,
|
||
|
|
int qidx, bool enable);
|
||
|
|
|
||
|
|
void nicvf_sq_enable(struct nicvf *nic, struct snd_queue *sq, int qidx);
|
||
|
|
void nicvf_sq_disable(struct nicvf *nic, int qidx);
|
||
|
|
void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt);
|
||
|
|
void nicvf_sq_free_used_descs(struct net_device *netdev,
|
||
|
|
struct snd_queue *sq, int qidx);
|
||
|
|
int nicvf_sq_append_skb(struct nicvf *nic, struct snd_queue *sq,
|
||
|
|
struct sk_buff *skb, u8 sq_num);
|
||
|
|
int nicvf_xdp_sq_append_pkt(struct nicvf *nic, struct snd_queue *sq,
|
||
|
|
u64 bufaddr, u64 dma_addr, u16 len);
|
||
|
|
void nicvf_xdp_sq_doorbell(struct nicvf *nic, struct snd_queue *sq, int sq_num);
|
||
|
|
|
||
|
|
struct sk_buff *nicvf_get_rcv_skb(struct nicvf *nic,
|
||
|
|
struct cqe_rx_t *cqe_rx, bool xdp);
|
||
|
|
void nicvf_rbdr_task(struct tasklet_struct *t);
|
||
|
|
void nicvf_rbdr_work(struct work_struct *work);
|
||
|
|
|
||
|
|
void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx);
|
||
|
|
void nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx);
|
||
|
|
void nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx);
|
||
|
|
int nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx);
|
||
|
|
|
||
|
|
/* Register access APIs */
|
||
|
|
void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val);
|
||
|
|
u64 nicvf_reg_read(struct nicvf *nic, u64 offset);
|
||
|
|
void nicvf_qset_reg_write(struct nicvf *nic, u64 offset, u64 val);
|
||
|
|
u64 nicvf_qset_reg_read(struct nicvf *nic, u64 offset);
|
||
|
|
void nicvf_queue_reg_write(struct nicvf *nic, u64 offset,
|
||
|
|
u64 qidx, u64 val);
|
||
|
|
u64 nicvf_queue_reg_read(struct nicvf *nic,
|
||
|
|
u64 offset, u64 qidx);
|
||
|
|
|
||
|
|
/* Stats */
|
||
|
|
void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx);
|
||
|
|
void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx);
|
||
|
|
int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx);
|
||
|
|
int nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cqe_send_t *cqe_tx);
|
||
|
|
#endif /* NICVF_QUEUES_H */
|