299 lines
15 KiB
C
299 lines
15 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* $Date: 2006/04/28 19:20:17 $ $RCSfile: vsc7326_reg.h,v $ $Revision: 1.5 $ */
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#ifndef _VSC7321_REG_H_
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#define _VSC7321_REG_H_
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/* Register definitions for Vitesse VSC7321 (Meigs II) MAC
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*
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* Straight off the data sheet, VMDS-10038 Rev 2.0 and
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* PD0011-01-14-Meigs-II 2002-12-12
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*/
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/* Just 'cause it's in here doesn't mean it's used. */
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#define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1))
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/* System and CPU comm's registers */
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#define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */
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#define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */
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#define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */
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#define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */
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#define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */
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#define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */
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#define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */
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#define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */
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#define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */
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#define REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19) /* Clock Speed Selection */
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#define REG_SYS_CLK_SELECT CRA(0x7,0xf,0x1c) /* System Clock Select */
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#define REG_GPIO_CTRL CRA(0x7,0xf,0x1d) /* GPIO Control */
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#define REG_GPIO_OUT CRA(0x7,0xf,0x1e) /* GPIO Out */
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#define REG_GPIO_IN CRA(0x7,0xf,0x1f) /* GPIO In */
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#define REG_CPU_TRANSFER_SEL CRA(0x7,0xf,0x20) /* CPU Transfer Select */
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#define REG_LOCAL_DATA CRA(0x7,0xf,0xfe) /* Local CPU Data Register */
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#define REG_LOCAL_STATUS CRA(0x7,0xf,0xff) /* Local CPU Status Register */
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/* Aggregator registers */
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#define REG_AGGR_SETUP CRA(0x7,0x1,0x00) /* Aggregator Setup */
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#define REG_PMAP_TABLE CRA(0x7,0x1,0x01) /* Port map table */
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#define REG_MPLS_BIT0 CRA(0x7,0x1,0x08) /* MPLS bit0 position */
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#define REG_MPLS_BIT1 CRA(0x7,0x1,0x09) /* MPLS bit1 position */
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#define REG_MPLS_BIT2 CRA(0x7,0x1,0x0a) /* MPLS bit2 position */
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#define REG_MPLS_BIT3 CRA(0x7,0x1,0x0b) /* MPLS bit3 position */
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#define REG_MPLS_BITMASK CRA(0x7,0x1,0x0c) /* MPLS bit mask */
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#define REG_PRE_BIT0POS CRA(0x7,0x1,0x10) /* Preamble bit0 position */
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#define REG_PRE_BIT1POS CRA(0x7,0x1,0x11) /* Preamble bit1 position */
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#define REG_PRE_BIT2POS CRA(0x7,0x1,0x12) /* Preamble bit2 position */
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#define REG_PRE_BIT3POS CRA(0x7,0x1,0x13) /* Preamble bit3 position */
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#define REG_PRE_ERR_CNT CRA(0x7,0x1,0x14) /* Preamble parity error count */
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/* BIST registers */
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/*#define REG_RAM_BIST_CMD CRA(0x7,0x2,0x00)*/ /* RAM BIST Command Register */
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/*#define REG_RAM_BIST_RESULT CRA(0x7,0x2,0x01)*/ /* RAM BIST Read Status/Result */
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#define REG_RAM_BIST_CMD CRA(0x7,0x1,0x00) /* RAM BIST Command Register */
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#define REG_RAM_BIST_RESULT CRA(0x7,0x1,0x01) /* RAM BIST Read Status/Result */
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#define BIST_PORT_SELECT 0x00 /* BIST port select */
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#define BIST_COMMAND 0x01 /* BIST enable/disable */
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#define BIST_STATUS 0x02 /* BIST operation status */
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#define BIST_ERR_CNT_LSB 0x03 /* BIST error count lo 8b */
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#define BIST_ERR_CNT_MSB 0x04 /* BIST error count hi 8b */
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#define BIST_ERR_SEL_LSB 0x05 /* BIST error select lo 8b */
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#define BIST_ERR_SEL_MSB 0x06 /* BIST error select hi 8b */
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#define BIST_ERROR_STATE 0x07 /* BIST engine internal state */
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#define BIST_ERR_ADR0 0x08 /* BIST error address lo 8b */
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#define BIST_ERR_ADR1 0x09 /* BIST error address lomid 8b */
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#define BIST_ERR_ADR2 0x0a /* BIST error address himid 8b */
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#define BIST_ERR_ADR3 0x0b /* BIST error address hi 8b */
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/* FIFO registers
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* ie = 0 for ingress, 1 for egress
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* fn = FIFO number, 0-9
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*/
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#define REG_TEST(ie,fn) CRA(0x2,ie&1,0x00+fn) /* Mode & Test Register */
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#define REG_TOP_BOTTOM(ie,fn) CRA(0x2,ie&1,0x10+fn) /* FIFO Buffer Top & Bottom */
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#define REG_TAIL(ie,fn) CRA(0x2,ie&1,0x20+fn) /* FIFO Write Pointer */
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#define REG_HEAD(ie,fn) CRA(0x2,ie&1,0x30+fn) /* FIFO Read Pointer */
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#define REG_HIGH_LOW_WM(ie,fn) CRA(0x2,ie&1,0x40+fn) /* Flow Control Water Marks */
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#define REG_CT_THRHLD(ie,fn) CRA(0x2,ie&1,0x50+fn) /* Cut Through Threshold */
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#define REG_FIFO_DROP_CNT(ie,fn) CRA(0x2,ie&1,0x60+fn) /* Drop & CRC Error Counter */
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#define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn) /* Input Side Debug Counter */
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#define REG_BUCKI(fn) CRA(0x2,2,0x20+fn) /* Input Side Debug Counter */
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#define REG_BUCKE(fn) CRA(0x2,3,0x20+fn) /* Input Side Debug Counter */
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/* Traffic shaper buckets
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* ie = 0 for ingress, 1 for egress
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* bn = bucket number 0-10 (yes, 11 buckets)
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*/
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/* OK, this one's kinda ugly. Some hardware designers are perverse. */
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#define REG_TRAFFIC_SHAPER_BUCKET(ie,bn) CRA(0x2,ie&1,0x0a + (bn>7) | ((bn&7)<<4))
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#define REG_TRAFFIC_SHAPER_CONTROL(ie) CRA(0x2,ie&1,0x3b)
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#define REG_SRAM_ADR(ie) CRA(0x2,ie&1,0x0e) /* FIFO SRAM address */
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#define REG_SRAM_WR_STRB(ie) CRA(0x2,ie&1,0x1e) /* FIFO SRAM write strobe */
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#define REG_SRAM_RD_STRB(ie) CRA(0x2,ie&1,0x2e) /* FIFO SRAM read strobe */
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#define REG_SRAM_DATA_0(ie) CRA(0x2,ie&1,0x3e) /* FIFO SRAM data lo 8b */
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#define REG_SRAM_DATA_1(ie) CRA(0x2,ie&1,0x4e) /* FIFO SRAM data lomid 8b */
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#define REG_SRAM_DATA_2(ie) CRA(0x2,ie&1,0x5e) /* FIFO SRAM data himid 8b */
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#define REG_SRAM_DATA_3(ie) CRA(0x2,ie&1,0x6e) /* FIFO SRAM data hi 8b */
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#define REG_SRAM_DATA_BLK_TYPE(ie) CRA(0x2,ie&1,0x7e) /* FIFO SRAM tag */
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/* REG_ING_CONTROL equals REG_CONTROL with ie = 0, likewise REG_EGR_CONTROL is ie = 1 */
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#define REG_CONTROL(ie) CRA(0x2,ie&1,0x0f) /* FIFO control */
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#define REG_ING_CONTROL CRA(0x2,0x0,0x0f) /* Ingress control (alias) */
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#define REG_EGR_CONTROL CRA(0x2,0x1,0x0f) /* Egress control (alias) */
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#define REG_AGE_TIMER(ie) CRA(0x2,ie&1,0x1f) /* Aging timer */
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#define REG_AGE_INC(ie) CRA(0x2,ie&1,0x2f) /* Aging increment */
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#define DEBUG_OUT(ie) CRA(0x2,ie&1,0x3f) /* Output debug counter control */
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#define DEBUG_CNT(ie) CRA(0x2,ie&1,0x4f) /* Output debug counter */
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/* SPI4 interface */
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#define REG_SPI4_MISC CRA(0x5,0x0,0x00) /* Misc Register */
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#define REG_SPI4_STATUS CRA(0x5,0x0,0x01) /* CML Status */
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#define REG_SPI4_ING_SETUP0 CRA(0x5,0x0,0x02) /* Ingress Status Channel Setup */
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#define REG_SPI4_ING_SETUP1 CRA(0x5,0x0,0x03) /* Ingress Data Training Setup */
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#define REG_SPI4_ING_SETUP2 CRA(0x5,0x0,0x04) /* Ingress Data Burst Size Setup */
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#define REG_SPI4_EGR_SETUP0 CRA(0x5,0x0,0x05) /* Egress Status Channel Setup */
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#define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */
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#define REG_SPI4_DBG_SETUP CRA(0x5,0x0,0x1A) /* Debug counters setup */
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#define REG_SPI4_TEST CRA(0x5,0x0,0x20) /* Test Setup Register */
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#define REG_TPGEN_UP0 CRA(0x5,0x0,0x21) /* Test Pattern generator user pattern 0 */
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#define REG_TPGEN_UP1 CRA(0x5,0x0,0x22) /* Test Pattern generator user pattern 1 */
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#define REG_TPCHK_UP0 CRA(0x5,0x0,0x23) /* Test Pattern checker user pattern 0 */
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#define REG_TPCHK_UP1 CRA(0x5,0x0,0x24) /* Test Pattern checker user pattern 1 */
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#define REG_TPSAM_P0 CRA(0x5,0x0,0x25) /* Sampled pattern 0 */
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#define REG_TPSAM_P1 CRA(0x5,0x0,0x26) /* Sampled pattern 1 */
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#define REG_TPERR_CNT CRA(0x5,0x0,0x27) /* Pattern checker error counter */
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#define REG_SPI4_STICKY CRA(0x5,0x0,0x30) /* Sticky bits register */
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#define REG_SPI4_DBG_INH CRA(0x5,0x0,0x31) /* Core egress & ingress inhibit */
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#define REG_SPI4_DBG_STATUS CRA(0x5,0x0,0x32) /* Sampled ingress status */
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#define REG_SPI4_DBG_GRANT CRA(0x5,0x0,0x33) /* Ingress cranted credit value */
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#define REG_SPI4_DESKEW CRA(0x5,0x0,0x43) /* Ingress cranted credit value */
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/* 10GbE MAC Block Registers */
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/* Note that those registers that are exactly the same for 10GbE as for
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* tri-speed are only defined with the version that needs a port number.
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* Pass 0xa in those cases.
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*
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* Also note that despite the presence of a MAC address register, this part
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* does no ingress MAC address filtering. That register is used only for
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* pause frame detection and generation.
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*/
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/* 10GbE specific, and different from tri-speed */
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#define REG_MISC_10G CRA(0x1,0xa,0x00) /* Misc 10GbE setup */
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#define REG_PAUSE_10G CRA(0x1,0xa,0x01) /* Pause register */
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#define REG_NORMALIZER_10G CRA(0x1,0xa,0x05) /* 10G normalizer */
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#define REG_STICKY_RX CRA(0x1,0xa,0x06) /* RX debug register */
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#define REG_DENORM_10G CRA(0x1,0xa,0x07) /* Denormalizer */
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#define REG_STICKY_TX CRA(0x1,0xa,0x08) /* TX sticky bits */
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#define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) /* XGMII lane 0-3 debug */
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#define REG_MAX_RXLOW CRA(0x1,0xa,0x0b) /* XGMII lane 4-7 debug */
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#define REG_MAC_TX_STICKY CRA(0x1,0xa,0x0c) /* MAC Tx state sticky debug */
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#define REG_MAC_TX_RUNNING CRA(0x1,0xa,0x0d) /* MAC Tx state running debug */
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#define REG_TX_ABORT_AGE CRA(0x1,0xa,0x14) /* Aged Tx frames discarded */
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#define REG_TX_ABORT_SHORT CRA(0x1,0xa,0x15) /* Short Tx frames discarded */
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#define REG_TX_ABORT_TAXI CRA(0x1,0xa,0x16) /* Taxi error frames discarded */
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#define REG_TX_ABORT_UNDERRUN CRA(0x1,0xa,0x17) /* Tx Underrun abort counter */
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#define REG_TX_DENORM_DISCARD CRA(0x1,0xa,0x18) /* Tx denormalizer discards */
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#define REG_XAUI_STAT_A CRA(0x1,0xa,0x20) /* XAUI status A */
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#define REG_XAUI_STAT_B CRA(0x1,0xa,0x21) /* XAUI status B */
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#define REG_XAUI_STAT_C CRA(0x1,0xa,0x22) /* XAUI status C */
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#define REG_XAUI_CONF_A CRA(0x1,0xa,0x23) /* XAUI configuration A */
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#define REG_XAUI_CONF_B CRA(0x1,0xa,0x24) /* XAUI configuration B */
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#define REG_XAUI_CODE_GRP_CNT CRA(0x1,0xa,0x25) /* XAUI code group error count */
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#define REG_XAUI_CONF_TEST_A CRA(0x1,0xa,0x26) /* XAUI test register A */
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#define REG_PDERRCNT CRA(0x1,0xa,0x27) /* XAUI test register B */
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/* pn = port number 0-9 for tri-speed, 10 for 10GbE */
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/* Both tri-speed and 10GbE */
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#define REG_MAX_LEN(pn) CRA(0x1,pn,0x02) /* Max length */
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#define REG_MAC_HIGH_ADDR(pn) CRA(0x1,pn,0x03) /* Upper 24 bits of MAC addr */
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#define REG_MAC_LOW_ADDR(pn) CRA(0x1,pn,0x04) /* Lower 24 bits of MAC addr */
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/* tri-speed only
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* pn = port number, 0-9
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*/
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#define REG_MODE_CFG(pn) CRA(0x1,pn,0x00) /* Mode configuration */
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#define REG_PAUSE_CFG(pn) CRA(0x1,pn,0x01) /* Pause configuration */
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#define REG_NORMALIZER(pn) CRA(0x1,pn,0x05) /* Normalizer */
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#define REG_TBI_STATUS(pn) CRA(0x1,pn,0x06) /* TBI status */
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#define REG_PCS_STATUS_DBG(pn) CRA(0x1,pn,0x07) /* PCS status debug */
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#define REG_PCS_CTRL(pn) CRA(0x1,pn,0x08) /* PCS control */
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#define REG_TBI_CONFIG(pn) CRA(0x1,pn,0x09) /* TBI configuration */
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#define REG_STICK_BIT(pn) CRA(0x1,pn,0x0a) /* Sticky bits */
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#define REG_DEV_SETUP(pn) CRA(0x1,pn,0x0b) /* MAC clock/reset setup */
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#define REG_DROP_CNT(pn) CRA(0x1,pn,0x0c) /* Drop counter */
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#define REG_PORT_POS(pn) CRA(0x1,pn,0x0d) /* Preamble port position */
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#define REG_PORT_FAIL(pn) CRA(0x1,pn,0x0e) /* Preamble port position */
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#define REG_SERDES_CONF(pn) CRA(0x1,pn,0x0f) /* SerDes configuration */
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#define REG_SERDES_TEST(pn) CRA(0x1,pn,0x10) /* SerDes test */
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#define REG_SERDES_STAT(pn) CRA(0x1,pn,0x11) /* SerDes status */
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#define REG_SERDES_COM_CNT(pn) CRA(0x1,pn,0x12) /* SerDes comma counter */
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#define REG_DENORM(pn) CRA(0x1,pn,0x15) /* Frame denormalization */
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#define REG_DBG(pn) CRA(0x1,pn,0x16) /* Device 1G debug */
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#define REG_TX_IFG(pn) CRA(0x1,pn,0x18) /* Tx IFG config */
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#define REG_HDX(pn) CRA(0x1,pn,0x19) /* Half-duplex config */
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/* Statistics */
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/* CRA(0x4,pn,reg) */
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/* reg below */
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/* pn = port number, 0-a, a = 10GbE */
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enum {
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RxInBytes = 0x00, // # Rx in octets
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RxSymbolCarrier = 0x01, // Frames w/ symbol errors
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RxPause = 0x02, // # pause frames received
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RxUnsupOpcode = 0x03, // # control frames with unsupported opcode
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RxOkBytes = 0x04, // # octets in good frames
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RxBadBytes = 0x05, // # octets in bad frames
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RxUnicast = 0x06, // # good unicast frames
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RxMulticast = 0x07, // # good multicast frames
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RxBroadcast = 0x08, // # good broadcast frames
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Crc = 0x09, // # frames w/ bad CRC only
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RxAlignment = 0x0a, // # frames w/ alignment err
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RxUndersize = 0x0b, // # frames undersize
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RxFragments = 0x0c, // # frames undersize w/ crc err
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RxInRangeLengthError = 0x0d, // # frames with length error
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RxOutOfRangeError = 0x0e, // # frames with illegal length field
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RxOversize = 0x0f, // # frames oversize
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RxJabbers = 0x10, // # frames oversize w/ crc err
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RxSize64 = 0x11, // # frames 64 octets long
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RxSize65To127 = 0x12, // # frames 65-127 octets
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RxSize128To255 = 0x13, // # frames 128-255
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|
RxSize256To511 = 0x14, // # frames 256-511
|
||
|
|
RxSize512To1023 = 0x15, // # frames 512-1023
|
||
|
|
RxSize1024To1518 = 0x16, // # frames 1024-1518
|
||
|
|
RxSize1519ToMax = 0x17, // # frames 1519-max
|
||
|
|
|
||
|
|
TxOutBytes = 0x18, // # octets tx
|
||
|
|
TxPause = 0x19, // # pause frames sent
|
||
|
|
TxOkBytes = 0x1a, // # octets tx OK
|
||
|
|
TxUnicast = 0x1b, // # frames unicast
|
||
|
|
TxMulticast = 0x1c, // # frames multicast
|
||
|
|
TxBroadcast = 0x1d, // # frames broadcast
|
||
|
|
TxMultipleColl = 0x1e, // # frames tx after multiple collisions
|
||
|
|
TxLateColl = 0x1f, // # late collisions detected
|
||
|
|
TxXcoll = 0x20, // # frames lost, excessive collisions
|
||
|
|
TxDefer = 0x21, // # frames deferred on first tx attempt
|
||
|
|
TxXdefer = 0x22, // # frames excessively deferred
|
||
|
|
TxCsense = 0x23, // carrier sense errors at frame end
|
||
|
|
TxSize64 = 0x24, // # frames 64 octets long
|
||
|
|
TxSize65To127 = 0x25, // # frames 65-127 octets
|
||
|
|
TxSize128To255 = 0x26, // # frames 128-255
|
||
|
|
TxSize256To511 = 0x27, // # frames 256-511
|
||
|
|
TxSize512To1023 = 0x28, // # frames 512-1023
|
||
|
|
TxSize1024To1518 = 0x29, // # frames 1024-1518
|
||
|
|
TxSize1519ToMax = 0x2a, // # frames 1519-max
|
||
|
|
TxSingleColl = 0x2b, // # frames tx after single collision
|
||
|
|
TxBackoff2 = 0x2c, // # frames tx ok after 2 backoffs/collisions
|
||
|
|
TxBackoff3 = 0x2d, // after 3 backoffs/collisions
|
||
|
|
TxBackoff4 = 0x2e, // after 4
|
||
|
|
TxBackoff5 = 0x2f, // after 5
|
||
|
|
TxBackoff6 = 0x30, // after 6
|
||
|
|
TxBackoff7 = 0x31, // after 7
|
||
|
|
TxBackoff8 = 0x32, // after 8
|
||
|
|
TxBackoff9 = 0x33, // after 9
|
||
|
|
TxBackoff10 = 0x34, // after 10
|
||
|
|
TxBackoff11 = 0x35, // after 11
|
||
|
|
TxBackoff12 = 0x36, // after 12
|
||
|
|
TxBackoff13 = 0x37, // after 13
|
||
|
|
TxBackoff14 = 0x38, // after 14
|
||
|
|
TxBackoff15 = 0x39, // after 15
|
||
|
|
TxUnderrun = 0x3a, // # frames dropped from underrun
|
||
|
|
// Hole. See REG_RX_XGMII_PROT_ERR below.
|
||
|
|
RxIpgShrink = 0x3c, // # of IPG shrinks detected
|
||
|
|
// Duplicate. See REG_STAT_STICKY10G below.
|
||
|
|
StatSticky1G = 0x3e, // tri-speed sticky bits
|
||
|
|
StatInit = 0x3f // Clear all statistics
|
||
|
|
};
|
||
|
|
|
||
|
|
#define REG_RX_XGMII_PROT_ERR CRA(0x4,0xa,0x3b) /* # protocol errors detected on XGMII interface */
|
||
|
|
#define REG_STAT_STICKY10G CRA(0x4,0xa,StatSticky1G) /* 10GbE sticky bits */
|
||
|
|
|
||
|
|
#define REG_RX_OK_BYTES(pn) CRA(0x4,pn,RxOkBytes)
|
||
|
|
#define REG_RX_BAD_BYTES(pn) CRA(0x4,pn,RxBadBytes)
|
||
|
|
#define REG_TX_OK_BYTES(pn) CRA(0x4,pn,TxOkBytes)
|
||
|
|
|
||
|
|
/* MII-Management Block registers */
|
||
|
|
/* These are for MII-M interface 0, which is the bidirectional LVTTL one. If
|
||
|
|
* we hooked up to the one with separate directions, the middle 0x0 needs to
|
||
|
|
* change to 0x1. And the current errata states that MII-M 1 doesn't work.
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define REG_MIIM_STATUS CRA(0x3,0x0,0x00) /* MII-M Status */
|
||
|
|
#define REG_MIIM_CMD CRA(0x3,0x0,0x01) /* MII-M Command */
|
||
|
|
#define REG_MIIM_DATA CRA(0x3,0x0,0x02) /* MII-M Data */
|
||
|
|
#define REG_MIIM_PRESCALE CRA(0x3,0x0,0x03) /* MII-M MDC Prescale */
|
||
|
|
|
||
|
|
#define REG_ING_FFILT_UM_EN CRA(0x2, 0, 0xd)
|
||
|
|
#define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d)
|
||
|
|
#define REG_ING_FFILT_VAL0 CRA(0x2, 0, 0x2d)
|
||
|
|
#define REG_ING_FFILT_VAL1 CRA(0x2, 0, 0x3d)
|
||
|
|
#define REG_ING_FFILT_MASK0 CRA(0x2, 0, 0x4d)
|
||
|
|
#define REG_ING_FFILT_MASK1 CRA(0x2, 0, 0x5d)
|
||
|
|
#define REG_ING_FFILT_MASK2 CRA(0x2, 0, 0x6d)
|
||
|
|
#define REG_ING_FFILT_ETYPE CRA(0x2, 0, 0x7d)
|
||
|
|
|
||
|
|
|
||
|
|
/* Whew. */
|
||
|
|
|
||
|
|
#endif
|