372 lines
12 KiB
C
372 lines
12 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2005-2016 Broadcom.
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* All rights reserved.
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*
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* Contact Information:
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* linux-drivers@emulex.com
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*
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* Emulex
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* 3333 Susan Street
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* Costa Mesa, CA 92626
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*/
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/********* Mailbox door bell *************/
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/* Used for driver communication with the FW.
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* The software must write this register twice to post any command. First,
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* it writes the register with hi=1 and the upper bits of the physical address
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* for the MAILBOX structure. Software must poll the ready bit until this
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* is acknowledged. Then, sotware writes the register with hi=0 with the lower
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* bits in the address. It must poll the ready bit until the command is
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* complete. Upon completion, the MAILBOX will contain a valid completion
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* queue entry.
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*/
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#define MPU_MAILBOX_DB_OFFSET 0x160
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#define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
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#define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
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#define MPU_EP_CONTROL 0
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/********** MPU semphore: used for SH & BE *************/
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#define SLIPORT_SOFTRESET_OFFSET 0x5c /* CSR BAR offset */
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#define SLIPORT_SEMAPHORE_OFFSET_BEx 0xac /* CSR BAR offset */
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#define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
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#define POST_STAGE_MASK 0x0000FFFF
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#define POST_ERR_MASK 0x1
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#define POST_ERR_SHIFT 31
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#define POST_ERR_RECOVERY_CODE_MASK 0xFFF
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/* Soft Reset register masks */
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#define SLIPORT_SOFTRESET_SR_MASK 0x00000080 /* SR bit */
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/* MPU semphore POST stage values */
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#define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
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#define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
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#define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
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#define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
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#define POST_STAGE_RECOVERABLE_ERR 0xE000 /* Recoverable err detected */
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/* FW has detected a UE and is dumping FAT log data */
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#define POST_STAGE_FAT_LOG_START 0x0D00
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#define POST_STAGE_ARMFW_UE 0xF000 /*FW has asserted an UE*/
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/* Lancer SLIPORT registers */
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#define SLIPORT_STATUS_OFFSET 0x404
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#define SLIPORT_CONTROL_OFFSET 0x408
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#define SLIPORT_ERROR1_OFFSET 0x40C
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#define SLIPORT_ERROR2_OFFSET 0x410
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#define PHYSDEV_CONTROL_OFFSET 0x414
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#define SLIPORT_STATUS_ERR_MASK 0x80000000
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#define SLIPORT_STATUS_DIP_MASK 0x02000000
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#define SLIPORT_STATUS_RN_MASK 0x01000000
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#define SLIPORT_STATUS_RDY_MASK 0x00800000
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#define SLI_PORT_CONTROL_IP_MASK 0x08000000
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#define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002
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#define PHYSDEV_CONTROL_DD_MASK 0x00000004
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#define PHYSDEV_CONTROL_INP_MASK 0x40000000
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#define SLIPORT_ERROR_NO_RESOURCE1 0x2
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#define SLIPORT_ERROR_NO_RESOURCE2 0x9
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#define SLIPORT_ERROR_FW_RESET1 0x2
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#define SLIPORT_ERROR_FW_RESET2 0x0
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/********* Memory BAR register ************/
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#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
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/* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
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* Disable" may still globally block interrupts in addition to individual
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* interrupt masks; a mechanism for the device driver to block all interrupts
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* atomically without having to arbitrate for the PCI Interrupt Disable bit
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* with the OS.
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*/
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#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK BIT(29) /* bit 29 */
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/********* PCI Function Capability *********/
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#define BE_FUNCTION_CAPS_RSS 0x2
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#define BE_FUNCTION_CAPS_SUPER_NIC 0x40
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/********* Power management (WOL) **********/
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#define PCICFG_PM_CONTROL_OFFSET 0x44
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#define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
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/********* Online Control Registers *******/
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#define PCICFG_ONLINE0 0xB0
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#define PCICFG_ONLINE1 0xB4
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/********* UE Status and Mask Registers ***/
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#define PCICFG_UE_STATUS_LOW 0xA0
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#define PCICFG_UE_STATUS_HIGH 0xA4
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#define PCICFG_UE_STATUS_LOW_MASK 0xA8
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#define PCICFG_UE_STATUS_HI_MASK 0xAC
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/******** SLI_INTF ***********************/
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#define SLI_INTF_REG_OFFSET 0x58
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#define SLI_INTF_VALID_MASK 0xE0000000
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#define SLI_INTF_VALID 0xC0000000
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#define SLI_INTF_HINT2_MASK 0x1F000000
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#define SLI_INTF_HINT2_SHIFT 24
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#define SLI_INTF_HINT1_MASK 0x00FF0000
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#define SLI_INTF_HINT1_SHIFT 16
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#define SLI_INTF_FAMILY_MASK 0x00000F00
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#define SLI_INTF_FAMILY_SHIFT 8
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#define SLI_INTF_IF_TYPE_MASK 0x0000F000
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#define SLI_INTF_IF_TYPE_SHIFT 12
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#define SLI_INTF_REV_MASK 0x000000F0
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#define SLI_INTF_REV_SHIFT 4
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#define SLI_INTF_FT_MASK 0x00000001
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#define SLI_INTF_TYPE_2 2
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#define SLI_INTF_TYPE_3 3
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/********* ISR0 Register offset **********/
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#define CEV_ISR0_OFFSET 0xC18
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#define CEV_ISR_SIZE 4
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/********* Event Q door bell *************/
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#define DB_EQ_OFFSET DB_CQ_OFFSET
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#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
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#define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
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#define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */
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/* Clear the interrupt for this eq */
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#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
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/* Must be 1 */
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#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
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/* Number of event entries processed */
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#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
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/* Rearm bit */
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#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
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/* Rearm to interrupt delay encoding */
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#define DB_EQ_R2I_DLY_SHIFT (30) /* bits 30 - 31 */
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/* Rearm to interrupt (R2I) delay multiplier encoding represents 3 different
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* values configured in CEV_REARM2IRPT_DLY_MULT_CSR register. This value is
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* programmed by host driver while ringing an EQ doorbell(EQ_DB) if a delay
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* between rearming the EQ and next interrupt on this EQ is desired.
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*/
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#define R2I_DLY_ENC_0 0 /* No delay */
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#define R2I_DLY_ENC_1 1 /* maps to 160us EQ delay */
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#define R2I_DLY_ENC_2 2 /* maps to 96us EQ delay */
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#define R2I_DLY_ENC_3 3 /* maps to 48us EQ delay */
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/********* Compl Q door bell *************/
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#define DB_CQ_OFFSET 0x120
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#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
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#define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */
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#define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14
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placing at 11-15 */
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/* Number of event entries processed */
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#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
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/* Rearm bit */
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#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
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/********** TX ULP door bell *************/
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#define DB_TXULP1_OFFSET 0x60
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#define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
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/* Number of tx entries posted */
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#define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
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#define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
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/********** RQ(erx) door bell ************/
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#define DB_RQ_OFFSET 0x100
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#define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
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/* Number of rx frags posted */
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#define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
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/********** MCC door bell ************/
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#define DB_MCCQ_OFFSET 0x140
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#define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
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/* Number of entries posted */
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#define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
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/********** SRIOV VF PCICFG OFFSET ********/
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#define SRIOV_VF_PCICFG_OFFSET (4096)
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/********** FAT TABLE ********/
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#define RETRIEVE_FAT 0
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#define QUERY_FAT 1
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/************* Rx Packet Type Encoding **************/
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#define BE_UNICAST_PACKET 0
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#define BE_MULTICAST_PACKET 1
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#define BE_BROADCAST_PACKET 2
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#define BE_RSVD_PACKET 3
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/*
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* BE descriptors: host memory data structures whose formats
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* are hardwired in BE silicon.
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*/
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/* Event Queue Descriptor */
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#define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
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#define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
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#define EQ_ENTRY_RES_ID_SHIFT 16
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struct be_eq_entry {
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u32 evt;
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};
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/* TX Queue Descriptor */
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#define ETH_WRB_FRAG_LEN_MASK 0xFFFF
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struct be_eth_wrb {
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__le32 frag_pa_hi; /* dword 0 */
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__le32 frag_pa_lo; /* dword 1 */
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u32 rsvd0; /* dword 2 */
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__le32 frag_len; /* dword 3: bits 0 - 15 */
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} __packed;
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/* Pseudo amap definition for eth_hdr_wrb in which each bit of the
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* actual structure is defined as a byte : used to calculate
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* offset/shift/mask of each field */
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struct amap_eth_hdr_wrb {
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u8 rsvd0[32]; /* dword 0 */
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u8 rsvd1[32]; /* dword 1 */
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u8 complete; /* dword 2 */
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u8 event;
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u8 crc;
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u8 forward;
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u8 lso6;
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u8 mgmt;
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u8 ipcs;
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u8 udpcs;
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u8 tcpcs;
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u8 lso;
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u8 vlan;
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u8 gso[2];
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u8 num_wrb[5];
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u8 lso_mss[14];
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u8 len[16]; /* dword 3 */
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u8 vlan_tag[16];
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} __packed;
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#define TX_HDR_WRB_COMPL 1 /* word 2 */
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#define TX_HDR_WRB_EVT BIT(1) /* word 2 */
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#define TX_HDR_WRB_NUM_SHIFT 13 /* word 2: bits 13:17 */
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#define TX_HDR_WRB_NUM_MASK 0x1F /* word 2: bits 13:17 */
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struct be_eth_hdr_wrb {
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__le32 dw[4];
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};
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/********* Tx Compl Status Encoding *********/
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#define BE_TX_COMP_HDR_PARSE_ERR 0x2
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#define BE_TX_COMP_NDMA_ERR 0x3
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#define BE_TX_COMP_ACL_ERR 0x5
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#define LANCER_TX_COMP_LSO_ERR 0x1
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#define LANCER_TX_COMP_HSW_DROP_MAC_ERR 0x3
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#define LANCER_TX_COMP_HSW_DROP_VLAN_ERR 0x5
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#define LANCER_TX_COMP_QINQ_ERR 0x7
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#define LANCER_TX_COMP_SGE_ERR 0x9
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#define LANCER_TX_COMP_PARITY_ERR 0xb
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#define LANCER_TX_COMP_DMA_ERR 0xd
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/* TX Compl Queue Descriptor */
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/* Pseudo amap definition for eth_tx_compl in which each bit of the
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* actual structure is defined as a byte: used to calculate
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* offset/shift/mask of each field */
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struct amap_eth_tx_compl {
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u8 wrb_index[16]; /* dword 0 */
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u8 ct[2]; /* dword 0 */
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u8 port[2]; /* dword 0 */
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u8 rsvd0[8]; /* dword 0 */
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u8 status[4]; /* dword 0 */
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u8 user_bytes[16]; /* dword 1 */
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u8 nwh_bytes[8]; /* dword 1 */
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u8 lso; /* dword 1 */
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u8 cast_enc[2]; /* dword 1 */
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u8 rsvd1[5]; /* dword 1 */
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u8 rsvd2[32]; /* dword 2 */
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u8 pkts[16]; /* dword 3 */
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u8 ringid[11]; /* dword 3 */
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u8 hash_val[4]; /* dword 3 */
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u8 valid; /* dword 3 */
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} __packed;
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struct be_eth_tx_compl {
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u32 dw[4];
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};
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/* RX Queue Descriptor */
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struct be_eth_rx_d {
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u32 fragpa_hi;
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u32 fragpa_lo;
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};
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/* RX Compl Queue Descriptor */
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/* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which
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* each bit of the actual structure is defined as a byte: used to calculate
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* offset/shift/mask of each field */
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struct amap_eth_rx_compl_v0 {
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u8 vlan_tag[16]; /* dword 0 */
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u8 pktsize[14]; /* dword 0 */
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u8 port; /* dword 0 */
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u8 ip_opt; /* dword 0 */
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u8 err; /* dword 1 */
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u8 rsshp; /* dword 1 */
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u8 ipf; /* dword 1 */
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u8 tcpf; /* dword 1 */
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u8 udpf; /* dword 1 */
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u8 ipcksm; /* dword 1 */
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u8 l4_cksm; /* dword 1 */
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u8 ip_version; /* dword 1 */
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u8 macdst[6]; /* dword 1 */
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u8 vtp; /* dword 1 */
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u8 ip_frag; /* dword 1 */
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u8 fragndx[10]; /* dword 1 */
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u8 ct[2]; /* dword 1 */
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u8 sw; /* dword 1 */
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u8 numfrags[3]; /* dword 1 */
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u8 rss_flush; /* dword 2 */
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u8 cast_enc[2]; /* dword 2 */
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u8 qnq; /* dword 2 */
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u8 rss_bank; /* dword 2 */
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u8 rsvd1[23]; /* dword 2 */
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u8 lro_pkt; /* dword 2 */
|
||
|
|
u8 rsvd2[2]; /* dword 2 */
|
||
|
|
u8 valid; /* dword 2 */
|
||
|
|
u8 rsshash[32]; /* dword 3 */
|
||
|
|
} __packed;
|
||
|
|
|
||
|
|
/* Pseudo amap definition for BE3 native mode eth_rx_compl in which
|
||
|
|
* each bit of the actual structure is defined as a byte: used to calculate
|
||
|
|
* offset/shift/mask of each field */
|
||
|
|
struct amap_eth_rx_compl_v1 {
|
||
|
|
u8 vlan_tag[16]; /* dword 0 */
|
||
|
|
u8 pktsize[14]; /* dword 0 */
|
||
|
|
u8 vtp; /* dword 0 */
|
||
|
|
u8 ip_opt; /* dword 0 */
|
||
|
|
u8 err; /* dword 1 */
|
||
|
|
u8 rsshp; /* dword 1 */
|
||
|
|
u8 ipf; /* dword 1 */
|
||
|
|
u8 tcpf; /* dword 1 */
|
||
|
|
u8 udpf; /* dword 1 */
|
||
|
|
u8 ipcksm; /* dword 1 */
|
||
|
|
u8 l4_cksm; /* dword 1 */
|
||
|
|
u8 ip_version; /* dword 1 */
|
||
|
|
u8 macdst[7]; /* dword 1 */
|
||
|
|
u8 rsvd0; /* dword 1 */
|
||
|
|
u8 fragndx[10]; /* dword 1 */
|
||
|
|
u8 ct[2]; /* dword 1 */
|
||
|
|
u8 sw; /* dword 1 */
|
||
|
|
u8 numfrags[3]; /* dword 1 */
|
||
|
|
u8 rss_flush; /* dword 2 */
|
||
|
|
u8 cast_enc[2]; /* dword 2 */
|
||
|
|
u8 qnq; /* dword 2 */
|
||
|
|
u8 rss_bank; /* dword 2 */
|
||
|
|
u8 port[2]; /* dword 2 */
|
||
|
|
u8 vntagp; /* dword 2 */
|
||
|
|
u8 header_len[8]; /* dword 2 */
|
||
|
|
u8 header_split[2]; /* dword 2 */
|
||
|
|
u8 rsvd1[12]; /* dword 2 */
|
||
|
|
u8 tunneled;
|
||
|
|
u8 valid; /* dword 2 */
|
||
|
|
u8 rsshash[32]; /* dword 3 */
|
||
|
|
} __packed;
|
||
|
|
|
||
|
|
struct be_eth_rx_compl {
|
||
|
|
u32 dw[4];
|
||
|
|
};
|