525 lines
14 KiB
C
525 lines
14 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2013 - 2018 Intel Corporation. */
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#include "fm10k_common.h"
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/**
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* fm10k_get_bus_info_generic - Generic set PCI bus info
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* @hw: pointer to hardware structure
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*
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* Gets the PCI bus info (speed, width, type) then calls helper function to
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* store this data within the fm10k_hw structure.
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**/
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s32 fm10k_get_bus_info_generic(struct fm10k_hw *hw)
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{
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u16 link_cap, link_status, device_cap, device_control;
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/* Get the maximum link width and speed from PCIe config space */
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link_cap = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_LINK_CAP);
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switch (link_cap & FM10K_PCIE_LINK_WIDTH) {
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case FM10K_PCIE_LINK_WIDTH_1:
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hw->bus_caps.width = fm10k_bus_width_pcie_x1;
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break;
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case FM10K_PCIE_LINK_WIDTH_2:
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hw->bus_caps.width = fm10k_bus_width_pcie_x2;
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break;
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case FM10K_PCIE_LINK_WIDTH_4:
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hw->bus_caps.width = fm10k_bus_width_pcie_x4;
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break;
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case FM10K_PCIE_LINK_WIDTH_8:
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hw->bus_caps.width = fm10k_bus_width_pcie_x8;
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break;
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default:
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hw->bus_caps.width = fm10k_bus_width_unknown;
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break;
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}
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switch (link_cap & FM10K_PCIE_LINK_SPEED) {
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case FM10K_PCIE_LINK_SPEED_2500:
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hw->bus_caps.speed = fm10k_bus_speed_2500;
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break;
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case FM10K_PCIE_LINK_SPEED_5000:
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hw->bus_caps.speed = fm10k_bus_speed_5000;
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break;
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case FM10K_PCIE_LINK_SPEED_8000:
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hw->bus_caps.speed = fm10k_bus_speed_8000;
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break;
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default:
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hw->bus_caps.speed = fm10k_bus_speed_unknown;
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break;
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}
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/* Get the PCIe maximum payload size for the PCIe function */
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device_cap = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_DEV_CAP);
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switch (device_cap & FM10K_PCIE_DEV_CAP_PAYLOAD) {
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case FM10K_PCIE_DEV_CAP_PAYLOAD_128:
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hw->bus_caps.payload = fm10k_bus_payload_128;
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break;
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case FM10K_PCIE_DEV_CAP_PAYLOAD_256:
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hw->bus_caps.payload = fm10k_bus_payload_256;
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break;
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case FM10K_PCIE_DEV_CAP_PAYLOAD_512:
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hw->bus_caps.payload = fm10k_bus_payload_512;
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break;
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default:
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hw->bus_caps.payload = fm10k_bus_payload_unknown;
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break;
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}
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/* Get the negotiated link width and speed from PCIe config space */
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link_status = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_LINK_STATUS);
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switch (link_status & FM10K_PCIE_LINK_WIDTH) {
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case FM10K_PCIE_LINK_WIDTH_1:
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hw->bus.width = fm10k_bus_width_pcie_x1;
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break;
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case FM10K_PCIE_LINK_WIDTH_2:
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hw->bus.width = fm10k_bus_width_pcie_x2;
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break;
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case FM10K_PCIE_LINK_WIDTH_4:
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hw->bus.width = fm10k_bus_width_pcie_x4;
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break;
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case FM10K_PCIE_LINK_WIDTH_8:
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hw->bus.width = fm10k_bus_width_pcie_x8;
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break;
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default:
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hw->bus.width = fm10k_bus_width_unknown;
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break;
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}
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switch (link_status & FM10K_PCIE_LINK_SPEED) {
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case FM10K_PCIE_LINK_SPEED_2500:
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hw->bus.speed = fm10k_bus_speed_2500;
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break;
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case FM10K_PCIE_LINK_SPEED_5000:
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hw->bus.speed = fm10k_bus_speed_5000;
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break;
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case FM10K_PCIE_LINK_SPEED_8000:
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hw->bus.speed = fm10k_bus_speed_8000;
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break;
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default:
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hw->bus.speed = fm10k_bus_speed_unknown;
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break;
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}
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/* Get the negotiated PCIe maximum payload size for the PCIe function */
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device_control = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_DEV_CTRL);
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switch (device_control & FM10K_PCIE_DEV_CTRL_PAYLOAD) {
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case FM10K_PCIE_DEV_CTRL_PAYLOAD_128:
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hw->bus.payload = fm10k_bus_payload_128;
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break;
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case FM10K_PCIE_DEV_CTRL_PAYLOAD_256:
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hw->bus.payload = fm10k_bus_payload_256;
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break;
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case FM10K_PCIE_DEV_CTRL_PAYLOAD_512:
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hw->bus.payload = fm10k_bus_payload_512;
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break;
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default:
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hw->bus.payload = fm10k_bus_payload_unknown;
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break;
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}
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return 0;
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}
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static u16 fm10k_get_pcie_msix_count_generic(struct fm10k_hw *hw)
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{
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u16 msix_count;
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/* read in value from MSI-X capability register */
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msix_count = fm10k_read_pci_cfg_word(hw, FM10K_PCI_MSIX_MSG_CTRL);
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msix_count &= FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK;
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/* MSI-X count is zero-based in HW */
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msix_count++;
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if (msix_count > FM10K_MAX_MSIX_VECTORS)
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msix_count = FM10K_MAX_MSIX_VECTORS;
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return msix_count;
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}
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/**
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* fm10k_get_invariants_generic - Inits constant values
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* @hw: pointer to the hardware structure
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*
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* Initialize the common invariants for the device.
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**/
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s32 fm10k_get_invariants_generic(struct fm10k_hw *hw)
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{
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struct fm10k_mac_info *mac = &hw->mac;
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/* initialize GLORT state to avoid any false hits */
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mac->dglort_map = FM10K_DGLORTMAP_NONE;
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/* record maximum number of MSI-X vectors */
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mac->max_msix_vectors = fm10k_get_pcie_msix_count_generic(hw);
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return 0;
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}
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/**
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* fm10k_start_hw_generic - Prepare hardware for Tx/Rx
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* @hw: pointer to hardware structure
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*
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* This function sets the Tx ready flag to indicate that the Tx path has
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* been initialized.
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**/
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s32 fm10k_start_hw_generic(struct fm10k_hw *hw)
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{
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/* set flag indicating we are beginning Tx */
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hw->mac.tx_ready = true;
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return 0;
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}
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/**
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* fm10k_disable_queues_generic - Stop Tx/Rx queues
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* @hw: pointer to hardware structure
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* @q_cnt: number of queues to be disabled
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*
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**/
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s32 fm10k_disable_queues_generic(struct fm10k_hw *hw, u16 q_cnt)
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{
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u32 reg;
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u16 i, time;
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/* clear tx_ready to prevent any false hits for reset */
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hw->mac.tx_ready = false;
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if (FM10K_REMOVED(hw->hw_addr))
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return 0;
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/* clear the enable bit for all rings */
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for (i = 0; i < q_cnt; i++) {
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reg = fm10k_read_reg(hw, FM10K_TXDCTL(i));
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fm10k_write_reg(hw, FM10K_TXDCTL(i),
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reg & ~FM10K_TXDCTL_ENABLE);
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reg = fm10k_read_reg(hw, FM10K_RXQCTL(i));
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fm10k_write_reg(hw, FM10K_RXQCTL(i),
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reg & ~FM10K_RXQCTL_ENABLE);
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}
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fm10k_write_flush(hw);
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udelay(1);
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/* loop through all queues to verify that they are all disabled */
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for (i = 0, time = FM10K_QUEUE_DISABLE_TIMEOUT; time;) {
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/* if we are at end of rings all rings are disabled */
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if (i == q_cnt)
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return 0;
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/* if queue enables cleared, then move to next ring pair */
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reg = fm10k_read_reg(hw, FM10K_TXDCTL(i));
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if (!~reg || !(reg & FM10K_TXDCTL_ENABLE)) {
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reg = fm10k_read_reg(hw, FM10K_RXQCTL(i));
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if (!~reg || !(reg & FM10K_RXQCTL_ENABLE)) {
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i++;
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continue;
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}
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}
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/* decrement time and wait 1 usec */
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time--;
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if (time)
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udelay(1);
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}
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return FM10K_ERR_REQUESTS_PENDING;
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}
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/**
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* fm10k_stop_hw_generic - Stop Tx/Rx units
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* @hw: pointer to hardware structure
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*
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**/
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s32 fm10k_stop_hw_generic(struct fm10k_hw *hw)
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{
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return fm10k_disable_queues_generic(hw, hw->mac.max_queues);
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}
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/**
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* fm10k_read_hw_stats_32b - Reads value of 32-bit registers
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* @hw: pointer to the hardware structure
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* @addr: address of register containing a 32-bit value
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* @stat: pointer to structure holding hw stat information
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*
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* Function reads the content of the register and returns the delta
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* between the base and the current value.
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* **/
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u32 fm10k_read_hw_stats_32b(struct fm10k_hw *hw, u32 addr,
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struct fm10k_hw_stat *stat)
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{
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u32 delta = fm10k_read_reg(hw, addr) - stat->base_l;
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if (FM10K_REMOVED(hw->hw_addr))
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stat->base_h = 0;
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return delta;
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}
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/**
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* fm10k_read_hw_stats_48b - Reads value of 48-bit registers
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* @hw: pointer to the hardware structure
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* @addr: address of register containing the lower 32-bit value
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* @stat: pointer to structure holding hw stat information
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*
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* Function reads the content of 2 registers, combined to represent a 48-bit
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* statistical value. Extra processing is required to handle overflowing.
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* Finally, a delta value is returned representing the difference between the
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* values stored in registers and values stored in the statistic counters.
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* **/
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static u64 fm10k_read_hw_stats_48b(struct fm10k_hw *hw, u32 addr,
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struct fm10k_hw_stat *stat)
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{
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u32 count_l;
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u32 count_h;
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u32 count_tmp;
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u64 delta;
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count_h = fm10k_read_reg(hw, addr + 1);
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/* Check for overflow */
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do {
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count_tmp = count_h;
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count_l = fm10k_read_reg(hw, addr);
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count_h = fm10k_read_reg(hw, addr + 1);
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} while (count_h != count_tmp);
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delta = ((u64)(count_h - stat->base_h) << 32) + count_l;
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delta -= stat->base_l;
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return delta & FM10K_48_BIT_MASK;
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}
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/**
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* fm10k_update_hw_base_48b - Updates 48-bit statistic base value
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* @stat: pointer to the hardware statistic structure
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* @delta: value to be updated into the hardware statistic structure
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*
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* Function receives a value and determines if an update is required based on
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* a delta calculation. Only the base value will be updated.
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**/
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static void fm10k_update_hw_base_48b(struct fm10k_hw_stat *stat, u64 delta)
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{
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if (!delta)
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return;
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/* update lower 32 bits */
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delta += stat->base_l;
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stat->base_l = (u32)delta;
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/* update upper 32 bits */
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stat->base_h += (u32)(delta >> 32);
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}
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/**
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* fm10k_update_hw_stats_tx_q - Updates TX queue statistics counters
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* @hw: pointer to the hardware structure
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* @q: pointer to the ring of hardware statistics queue
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* @idx: index pointing to the start of the ring iteration
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*
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* Function updates the TX queue statistics counters that are related to the
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* hardware.
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**/
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static void fm10k_update_hw_stats_tx_q(struct fm10k_hw *hw,
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struct fm10k_hw_stats_q *q,
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u32 idx)
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{
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u32 id_tx, id_tx_prev, tx_packets;
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u64 tx_bytes = 0;
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/* Retrieve TX Owner Data */
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id_tx = fm10k_read_reg(hw, FM10K_TXQCTL(idx));
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/* Process TX Ring */
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do {
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tx_packets = fm10k_read_hw_stats_32b(hw, FM10K_QPTC(idx),
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&q->tx_packets);
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if (tx_packets)
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tx_bytes = fm10k_read_hw_stats_48b(hw,
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FM10K_QBTC_L(idx),
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&q->tx_bytes);
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/* Re-Check Owner Data */
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id_tx_prev = id_tx;
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id_tx = fm10k_read_reg(hw, FM10K_TXQCTL(idx));
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} while ((id_tx ^ id_tx_prev) & FM10K_TXQCTL_ID_MASK);
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/* drop non-ID bits and set VALID ID bit */
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id_tx &= FM10K_TXQCTL_ID_MASK;
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id_tx |= FM10K_STAT_VALID;
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/* update packet counts */
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|
if (q->tx_stats_idx == id_tx) {
|
||
|
|
q->tx_packets.count += tx_packets;
|
||
|
|
q->tx_bytes.count += tx_bytes;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* update bases and record ID */
|
||
|
|
fm10k_update_hw_base_32b(&q->tx_packets, tx_packets);
|
||
|
|
fm10k_update_hw_base_48b(&q->tx_bytes, tx_bytes);
|
||
|
|
|
||
|
|
q->tx_stats_idx = id_tx;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* fm10k_update_hw_stats_rx_q - Updates RX queue statistics counters
|
||
|
|
* @hw: pointer to the hardware structure
|
||
|
|
* @q: pointer to the ring of hardware statistics queue
|
||
|
|
* @idx: index pointing to the start of the ring iteration
|
||
|
|
*
|
||
|
|
* Function updates the RX queue statistics counters that are related to the
|
||
|
|
* hardware.
|
||
|
|
**/
|
||
|
|
static void fm10k_update_hw_stats_rx_q(struct fm10k_hw *hw,
|
||
|
|
struct fm10k_hw_stats_q *q,
|
||
|
|
u32 idx)
|
||
|
|
{
|
||
|
|
u32 id_rx, id_rx_prev, rx_packets, rx_drops;
|
||
|
|
u64 rx_bytes = 0;
|
||
|
|
|
||
|
|
/* Retrieve RX Owner Data */
|
||
|
|
id_rx = fm10k_read_reg(hw, FM10K_RXQCTL(idx));
|
||
|
|
|
||
|
|
/* Process RX Ring */
|
||
|
|
do {
|
||
|
|
rx_drops = fm10k_read_hw_stats_32b(hw, FM10K_QPRDC(idx),
|
||
|
|
&q->rx_drops);
|
||
|
|
|
||
|
|
rx_packets = fm10k_read_hw_stats_32b(hw, FM10K_QPRC(idx),
|
||
|
|
&q->rx_packets);
|
||
|
|
|
||
|
|
if (rx_packets)
|
||
|
|
rx_bytes = fm10k_read_hw_stats_48b(hw,
|
||
|
|
FM10K_QBRC_L(idx),
|
||
|
|
&q->rx_bytes);
|
||
|
|
|
||
|
|
/* Re-Check Owner Data */
|
||
|
|
id_rx_prev = id_rx;
|
||
|
|
id_rx = fm10k_read_reg(hw, FM10K_RXQCTL(idx));
|
||
|
|
} while ((id_rx ^ id_rx_prev) & FM10K_RXQCTL_ID_MASK);
|
||
|
|
|
||
|
|
/* drop non-ID bits and set VALID ID bit */
|
||
|
|
id_rx &= FM10K_RXQCTL_ID_MASK;
|
||
|
|
id_rx |= FM10K_STAT_VALID;
|
||
|
|
|
||
|
|
/* update packet counts */
|
||
|
|
if (q->rx_stats_idx == id_rx) {
|
||
|
|
q->rx_drops.count += rx_drops;
|
||
|
|
q->rx_packets.count += rx_packets;
|
||
|
|
q->rx_bytes.count += rx_bytes;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* update bases and record ID */
|
||
|
|
fm10k_update_hw_base_32b(&q->rx_drops, rx_drops);
|
||
|
|
fm10k_update_hw_base_32b(&q->rx_packets, rx_packets);
|
||
|
|
fm10k_update_hw_base_48b(&q->rx_bytes, rx_bytes);
|
||
|
|
|
||
|
|
q->rx_stats_idx = id_rx;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* fm10k_update_hw_stats_q - Updates queue statistics counters
|
||
|
|
* @hw: pointer to the hardware structure
|
||
|
|
* @q: pointer to the ring of hardware statistics queue
|
||
|
|
* @idx: index pointing to the start of the ring iteration
|
||
|
|
* @count: number of queues to iterate over
|
||
|
|
*
|
||
|
|
* Function updates the queue statistics counters that are related to the
|
||
|
|
* hardware.
|
||
|
|
**/
|
||
|
|
void fm10k_update_hw_stats_q(struct fm10k_hw *hw, struct fm10k_hw_stats_q *q,
|
||
|
|
u32 idx, u32 count)
|
||
|
|
{
|
||
|
|
u32 i;
|
||
|
|
|
||
|
|
for (i = 0; i < count; i++, idx++, q++) {
|
||
|
|
fm10k_update_hw_stats_tx_q(hw, q, idx);
|
||
|
|
fm10k_update_hw_stats_rx_q(hw, q, idx);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* fm10k_unbind_hw_stats_q - Unbind the queue counters from their queues
|
||
|
|
* @q: pointer to the ring of hardware statistics queue
|
||
|
|
* @idx: index pointing to the start of the ring iteration
|
||
|
|
* @count: number of queues to iterate over
|
||
|
|
*
|
||
|
|
* Function invalidates the index values for the queues so any updates that
|
||
|
|
* may have happened are ignored and the base for the queue stats is reset.
|
||
|
|
**/
|
||
|
|
void fm10k_unbind_hw_stats_q(struct fm10k_hw_stats_q *q, u32 idx, u32 count)
|
||
|
|
{
|
||
|
|
u32 i;
|
||
|
|
|
||
|
|
for (i = 0; i < count; i++, idx++, q++) {
|
||
|
|
q->rx_stats_idx = 0;
|
||
|
|
q->tx_stats_idx = 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* fm10k_get_host_state_generic - Returns the state of the host
|
||
|
|
* @hw: pointer to hardware structure
|
||
|
|
* @host_ready: pointer to boolean value that will record host state
|
||
|
|
*
|
||
|
|
* This function will check the health of the mailbox and Tx queue 0
|
||
|
|
* in order to determine if we should report that the link is up or not.
|
||
|
|
**/
|
||
|
|
s32 fm10k_get_host_state_generic(struct fm10k_hw *hw, bool *host_ready)
|
||
|
|
{
|
||
|
|
struct fm10k_mbx_info *mbx = &hw->mbx;
|
||
|
|
struct fm10k_mac_info *mac = &hw->mac;
|
||
|
|
s32 ret_val = 0;
|
||
|
|
u32 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(0));
|
||
|
|
|
||
|
|
/* process upstream mailbox in case interrupts were disabled */
|
||
|
|
mbx->ops.process(hw, mbx);
|
||
|
|
|
||
|
|
/* If Tx is no longer enabled link should come down */
|
||
|
|
if (!(~txdctl) || !(txdctl & FM10K_TXDCTL_ENABLE))
|
||
|
|
mac->get_host_state = true;
|
||
|
|
|
||
|
|
/* exit if not checking for link, or link cannot be changed */
|
||
|
|
if (!mac->get_host_state || !(~txdctl))
|
||
|
|
goto out;
|
||
|
|
|
||
|
|
/* if we somehow dropped the Tx enable we should reset */
|
||
|
|
if (mac->tx_ready && !(txdctl & FM10K_TXDCTL_ENABLE)) {
|
||
|
|
ret_val = FM10K_ERR_RESET_REQUESTED;
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if Mailbox timed out we should request reset */
|
||
|
|
if (!mbx->timeout) {
|
||
|
|
ret_val = FM10K_ERR_RESET_REQUESTED;
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* verify Mailbox is still open */
|
||
|
|
if (mbx->state != FM10K_STATE_OPEN)
|
||
|
|
goto out;
|
||
|
|
|
||
|
|
/* interface cannot receive traffic without logical ports */
|
||
|
|
if (mac->dglort_map == FM10K_DGLORTMAP_NONE) {
|
||
|
|
if (mac->ops.request_lport_map)
|
||
|
|
ret_val = mac->ops.request_lport_map(hw);
|
||
|
|
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if we passed all the tests above then the switch is ready and we no
|
||
|
|
* longer need to check for link
|
||
|
|
*/
|
||
|
|
mac->get_host_state = false;
|
||
|
|
|
||
|
|
out:
|
||
|
|
*host_ready = !mac->get_host_state;
|
||
|
|
return ret_val;
|
||
|
|
}
|