267 lines
6.7 KiB
C
267 lines
6.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell OcteonTx2 CGX driver
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*
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* Copyright (C) 2018 Marvell.
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*
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*/
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#ifndef __CGX_FW_INTF_H__
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#define __CGX_FW_INTF_H__
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#define CGX_FIRMWARE_MAJOR_VER 1
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#define CGX_FIRMWARE_MINOR_VER 0
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#define CGX_EVENT_ACK 1UL
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/* CGX error types. set for cmd response status as CGX_STAT_FAIL */
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enum cgx_error_type {
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CGX_ERR_NONE,
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CGX_ERR_LMAC_NOT_ENABLED,
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CGX_ERR_LMAC_MODE_INVALID,
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CGX_ERR_REQUEST_ID_INVALID,
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CGX_ERR_PREV_ACK_NOT_CLEAR,
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CGX_ERR_PHY_LINK_DOWN,
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CGX_ERR_PCS_RESET_FAIL,
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CGX_ERR_AN_CPT_FAIL,
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CGX_ERR_TX_NOT_IDLE,
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CGX_ERR_RX_NOT_IDLE,
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CGX_ERR_SPUX_BR_BLKLOCK_FAIL,
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CGX_ERR_SPUX_RX_ALIGN_FAIL,
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CGX_ERR_SPUX_TX_FAULT,
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CGX_ERR_SPUX_RX_FAULT,
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CGX_ERR_SPUX_RESET_FAIL,
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CGX_ERR_SPUX_AN_RESET_FAIL,
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CGX_ERR_SPUX_USX_AN_RESET_FAIL,
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CGX_ERR_SMUX_RX_LINK_NOT_OK,
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CGX_ERR_PCS_RECV_LINK_FAIL,
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CGX_ERR_TRAINING_FAIL,
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CGX_ERR_RX_EQU_FAIL,
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CGX_ERR_SPUX_BER_FAIL,
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CGX_ERR_SPUX_RSFEC_ALGN_FAIL,
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CGX_ERR_SPUX_MARKER_LOCK_FAIL,
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CGX_ERR_SET_FEC_INVALID,
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CGX_ERR_SET_FEC_FAIL,
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CGX_ERR_MODULE_INVALID,
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CGX_ERR_MODULE_NOT_PRESENT,
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CGX_ERR_SPEED_CHANGE_INVALID,
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};
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/* LINK speed types */
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enum cgx_link_speed {
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CGX_LINK_NONE,
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CGX_LINK_10M,
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CGX_LINK_100M,
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CGX_LINK_1G,
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CGX_LINK_2HG,
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CGX_LINK_5G,
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CGX_LINK_10G,
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CGX_LINK_20G,
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CGX_LINK_25G,
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CGX_LINK_40G,
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CGX_LINK_50G,
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CGX_LINK_80G,
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CGX_LINK_100G,
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CGX_LINK_SPEED_MAX,
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};
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enum CGX_MODE_ {
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CGX_MODE_SGMII,
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CGX_MODE_1000_BASEX,
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CGX_MODE_QSGMII,
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CGX_MODE_10G_C2C,
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CGX_MODE_10G_C2M,
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CGX_MODE_10G_KR,
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CGX_MODE_20G_C2C,
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CGX_MODE_25G_C2C,
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CGX_MODE_25G_C2M,
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CGX_MODE_25G_2_C2C,
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CGX_MODE_25G_CR,
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CGX_MODE_25G_KR,
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CGX_MODE_40G_C2C,
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CGX_MODE_40G_C2M,
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CGX_MODE_40G_CR4,
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CGX_MODE_40G_KR4,
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CGX_MODE_40GAUI_C2C,
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CGX_MODE_50G_C2C,
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CGX_MODE_50G_C2M,
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CGX_MODE_50G_4_C2C,
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CGX_MODE_50G_CR,
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CGX_MODE_50G_KR,
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CGX_MODE_80GAUI_C2C,
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CGX_MODE_100G_C2C,
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CGX_MODE_100G_C2M,
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CGX_MODE_100G_CR4,
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CGX_MODE_100G_KR4,
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CGX_MODE_MAX /* = 29 */
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};
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/* REQUEST ID types. Input to firmware */
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enum cgx_cmd_id {
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CGX_CMD_NONE,
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CGX_CMD_GET_FW_VER,
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CGX_CMD_GET_MAC_ADDR,
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CGX_CMD_SET_MTU,
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CGX_CMD_GET_LINK_STS, /* optional to user */
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CGX_CMD_LINK_BRING_UP,
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CGX_CMD_LINK_BRING_DOWN,
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CGX_CMD_INTERNAL_LBK,
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CGX_CMD_EXTERNAL_LBK,
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CGX_CMD_HIGIG,
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CGX_CMD_LINK_STAT_CHANGE,
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CGX_CMD_MODE_CHANGE, /* hot plug support */
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CGX_CMD_INTF_SHUTDOWN,
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CGX_CMD_GET_MKEX_PRFL_SIZE,
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CGX_CMD_GET_MKEX_PRFL_ADDR,
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CGX_CMD_GET_FWD_BASE, /* get base address of shared FW data */
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CGX_CMD_GET_LINK_MODES, /* Supported Link Modes */
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CGX_CMD_SET_LINK_MODE,
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CGX_CMD_GET_SUPPORTED_FEC,
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CGX_CMD_SET_FEC,
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CGX_CMD_GET_AN,
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CGX_CMD_SET_AN,
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CGX_CMD_GET_ADV_LINK_MODES,
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CGX_CMD_GET_ADV_FEC,
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CGX_CMD_GET_PHY_MOD_TYPE, /* line-side modulation type: NRZ or PAM4 */
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CGX_CMD_SET_PHY_MOD_TYPE,
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CGX_CMD_PRBS,
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CGX_CMD_DISPLAY_EYE,
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CGX_CMD_GET_PHY_FEC_STATS,
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};
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/* async event ids */
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enum cgx_evt_id {
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CGX_EVT_NONE,
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CGX_EVT_LINK_CHANGE,
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};
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/* event types - cause of interrupt */
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enum cgx_evt_type {
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CGX_EVT_ASYNC,
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CGX_EVT_CMD_RESP
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};
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enum cgx_stat {
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CGX_STAT_SUCCESS,
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CGX_STAT_FAIL
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};
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enum cgx_cmd_own {
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CGX_CMD_OWN_NS,
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CGX_CMD_OWN_FIRMWARE,
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};
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/* m - bit mask
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* y - value to be written in the bitrange
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* x - input value whose bitrange to be modified
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*/
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#define FIELD_SET(m, y, x) \
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(((x) & ~(m)) | \
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FIELD_PREP((m), (y)))
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/* scratchx(0) CSR used for ATF->non-secure SW communication.
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* This acts as the status register
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* Provides details on command ack/status, command response, error details
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*/
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#define EVTREG_ACK BIT_ULL(0)
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#define EVTREG_EVT_TYPE BIT_ULL(1)
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#define EVTREG_STAT BIT_ULL(2)
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#define EVTREG_ID GENMASK_ULL(8, 3)
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/* Response to command IDs with command status as CGX_STAT_FAIL
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*
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* Not applicable for commands :
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* CGX_CMD_LINK_BRING_UP/DOWN/CGX_EVT_LINK_CHANGE
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*/
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#define EVTREG_ERRTYPE GENMASK_ULL(18, 9)
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/* Response to cmd ID as CGX_CMD_GET_FW_VER with cmd status as
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* CGX_STAT_SUCCESS
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*/
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#define RESP_MAJOR_VER GENMASK_ULL(12, 9)
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#define RESP_MINOR_VER GENMASK_ULL(16, 13)
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/* Response to cmd ID as CGX_CMD_GET_MAC_ADDR with cmd status as
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* CGX_STAT_SUCCESS
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*/
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#define RESP_MAC_ADDR GENMASK_ULL(56, 9)
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/* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_SIZE with cmd status as
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* CGX_STAT_SUCCESS
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*/
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#define RESP_MKEX_PRFL_SIZE GENMASK_ULL(63, 9)
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/* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_ADDR with cmd status as
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* CGX_STAT_SUCCESS
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*/
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#define RESP_MKEX_PRFL_ADDR GENMASK_ULL(63, 9)
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/* Response to cmd ID as CGX_CMD_GET_FWD_BASE with cmd status as
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* CGX_STAT_SUCCESS
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*/
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#define RESP_FWD_BASE GENMASK_ULL(56, 9)
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#define RESP_LINKSTAT_LMAC_TYPE GENMASK_ULL(35, 28)
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/* Response to cmd ID - CGX_CMD_LINK_BRING_UP/DOWN, event ID CGX_EVT_LINK_CHANGE
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* status can be either CGX_STAT_FAIL or CGX_STAT_SUCCESS
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*
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* In case of CGX_STAT_FAIL, it indicates CGX configuration failed
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* when processing link up/down/change command.
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* Both err_type and current link status will be updated
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*
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* In case of CGX_STAT_SUCCESS, err_type will be CGX_ERR_NONE and current
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* link status will be updated
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*/
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struct cgx_lnk_sts {
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uint64_t reserved1:9;
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uint64_t link_up:1;
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uint64_t full_duplex:1;
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uint64_t speed:4; /* cgx_link_speed */
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uint64_t err_type:10;
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uint64_t an:1; /* AN supported or not */
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uint64_t fec:2; /* FEC type if enabled, if not 0 */
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uint64_t port:8;
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uint64_t reserved2:28;
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};
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#define RESP_LINKSTAT_UP GENMASK_ULL(9, 9)
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#define RESP_LINKSTAT_FDUPLEX GENMASK_ULL(10, 10)
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#define RESP_LINKSTAT_SPEED GENMASK_ULL(14, 11)
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#define RESP_LINKSTAT_ERRTYPE GENMASK_ULL(24, 15)
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#define RESP_LINKSTAT_AN GENMASK_ULL(25, 25)
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#define RESP_LINKSTAT_FEC GENMASK_ULL(27, 26)
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#define RESP_LINKSTAT_PORT GENMASK_ULL(35, 28)
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/* scratchx(1) CSR used for non-secure SW->ATF communication
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* This CSR acts as a command register
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*/
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#define CMDREG_OWN BIT_ULL(0)
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#define CMDREG_ID GENMASK_ULL(7, 2)
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/* Any command using enable/disable as an argument need
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* to set this bitfield.
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* Ex: Loopback, HiGig...
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*/
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#define CMDREG_ENABLE BIT_ULL(8)
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/* command argument to be passed for cmd ID - CGX_CMD_SET_MTU */
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#define CMDMTU_SIZE GENMASK_ULL(23, 8)
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/* command argument to be passed for cmd ID - CGX_CMD_LINK_CHANGE */
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#define CMDLINKCHANGE_LINKUP BIT_ULL(8)
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#define CMDLINKCHANGE_FULLDPLX BIT_ULL(9)
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#define CMDLINKCHANGE_SPEED GENMASK_ULL(13, 10)
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#define CMDSETFEC GENMASK_ULL(9, 8)
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/* command argument to be passed for cmd ID - CGX_CMD_MODE_CHANGE */
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#define CMDMODECHANGE_SPEED GENMASK_ULL(11, 8)
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#define CMDMODECHANGE_DUPLEX GENMASK_ULL(12, 12)
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#define CMDMODECHANGE_AN GENMASK_ULL(13, 13)
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#define CMDMODECHANGE_PORT GENMASK_ULL(21, 14)
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#define CMDMODECHANGE_FLAGS GENMASK_ULL(63, 22)
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/* LINK_BRING_UP command timeout */
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#define LINKCFG_TIMEOUT GENMASK_ULL(21, 8)
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#endif /* __CGX_FW_INTF_H__ */
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