471 lines
11 KiB
C
471 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/* Marvell RVU Ethernet driver
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*
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* Copyright (C) 2021 Marvell.
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*
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*/
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#include "otx2_common.h"
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static int otx2_check_pfc_config(struct otx2_nic *pfvf)
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{
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u8 tx_queues = pfvf->hw.tx_queues, prio;
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u8 pfc_en = pfvf->pfc_en;
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for (prio = 0; prio < NIX_PF_PFC_PRIO_MAX; prio++) {
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if ((pfc_en & (1 << prio)) &&
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prio > tx_queues - 1) {
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dev_warn(pfvf->dev,
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"Increase number of tx queues from %d to %d to support PFC.\n",
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tx_queues, prio + 1);
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return -EINVAL;
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}
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}
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return 0;
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}
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int otx2_pfc_txschq_config(struct otx2_nic *pfvf)
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{
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u8 pfc_en, pfc_bit_set;
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int prio, lvl, err;
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pfc_en = pfvf->pfc_en;
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for (prio = 0; prio < NIX_PF_PFC_PRIO_MAX; prio++) {
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pfc_bit_set = pfc_en & (1 << prio);
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/* Either PFC bit is not set
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* or tx scheduler is not allocated for the priority
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*/
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if (!pfc_bit_set || !pfvf->pfc_alloc_status[prio])
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continue;
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/* configure the scheduler for the tls*/
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for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
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err = otx2_txschq_config(pfvf, lvl, prio, true);
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if (err) {
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dev_err(pfvf->dev,
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"%s configure PFC tx schq for lvl:%d, prio:%d failed!\n",
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__func__, lvl, prio);
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return err;
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}
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}
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}
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return 0;
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}
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static int otx2_pfc_txschq_alloc_one(struct otx2_nic *pfvf, u8 prio)
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{
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struct nix_txsch_alloc_req *req;
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struct nix_txsch_alloc_rsp *rsp;
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int lvl, rc;
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/* Get memory to put this msg */
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req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox);
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if (!req)
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return -ENOMEM;
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/* Request one schq per level upto max level as configured
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* link config level. These rest of the scheduler can be
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* same as hw.txschq_list.
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*/
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for (lvl = 0; lvl < pfvf->hw.txschq_link_cfg_lvl; lvl++)
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req->schq[lvl] = 1;
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rc = otx2_sync_mbox_msg(&pfvf->mbox);
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if (rc)
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return rc;
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rsp = (struct nix_txsch_alloc_rsp *)
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otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
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if (IS_ERR(rsp))
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return PTR_ERR(rsp);
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/* Setup transmit scheduler list */
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for (lvl = 0; lvl < pfvf->hw.txschq_link_cfg_lvl; lvl++) {
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if (!rsp->schq[lvl])
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return -ENOSPC;
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pfvf->pfc_schq_list[lvl][prio] = rsp->schq_list[lvl][0];
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}
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/* Set the Tx schedulers for rest of the levels same as
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* hw.txschq_list as those will be common for all.
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*/
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for (; lvl < NIX_TXSCH_LVL_CNT; lvl++)
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pfvf->pfc_schq_list[lvl][prio] = pfvf->hw.txschq_list[lvl][0];
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pfvf->pfc_alloc_status[prio] = true;
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return 0;
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}
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int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf)
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{
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u8 pfc_en = pfvf->pfc_en;
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u8 pfc_bit_set;
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int err, prio;
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for (prio = 0; prio < NIX_PF_PFC_PRIO_MAX; prio++) {
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pfc_bit_set = pfc_en & (1 << prio);
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if (!pfc_bit_set || pfvf->pfc_alloc_status[prio])
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continue;
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/* Add new scheduler to the priority */
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err = otx2_pfc_txschq_alloc_one(pfvf, prio);
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if (err) {
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dev_err(pfvf->dev, "%s failed to allocate PFC TX schedulers\n", __func__);
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return err;
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}
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}
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return 0;
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}
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static int otx2_pfc_txschq_stop_one(struct otx2_nic *pfvf, u8 prio)
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{
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struct nix_txsch_free_req *free_req;
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mutex_lock(&pfvf->mbox.lock);
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/* free PFC TLx nodes */
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free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox);
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if (!free_req) {
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mutex_unlock(&pfvf->mbox.lock);
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return -ENOMEM;
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}
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free_req->flags = TXSCHQ_FREE_ALL;
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otx2_sync_mbox_msg(&pfvf->mbox);
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mutex_unlock(&pfvf->mbox.lock);
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pfvf->pfc_alloc_status[prio] = false;
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return 0;
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}
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static int otx2_pfc_update_sq_smq_mapping(struct otx2_nic *pfvf, int prio)
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{
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struct nix_cn10k_aq_enq_req *cn10k_sq_aq;
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struct net_device *dev = pfvf->netdev;
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bool if_up = netif_running(dev);
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struct nix_aq_enq_req *sq_aq;
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if (if_up) {
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if (pfvf->pfc_alloc_status[prio])
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netif_tx_stop_all_queues(pfvf->netdev);
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else
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netif_tx_stop_queue(netdev_get_tx_queue(dev, prio));
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}
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if (test_bit(CN10K_LMTST, &pfvf->hw.cap_flag)) {
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cn10k_sq_aq = otx2_mbox_alloc_msg_nix_cn10k_aq_enq(&pfvf->mbox);
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if (!cn10k_sq_aq)
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return -ENOMEM;
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/* Fill AQ info */
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cn10k_sq_aq->qidx = prio;
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cn10k_sq_aq->ctype = NIX_AQ_CTYPE_SQ;
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cn10k_sq_aq->op = NIX_AQ_INSTOP_WRITE;
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/* Fill fields to update */
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cn10k_sq_aq->sq.ena = 1;
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cn10k_sq_aq->sq_mask.ena = 1;
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cn10k_sq_aq->sq_mask.smq = GENMASK(9, 0);
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cn10k_sq_aq->sq.smq = otx2_get_smq_idx(pfvf, prio);
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} else {
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sq_aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
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if (!sq_aq)
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return -ENOMEM;
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/* Fill AQ info */
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sq_aq->qidx = prio;
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sq_aq->ctype = NIX_AQ_CTYPE_SQ;
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sq_aq->op = NIX_AQ_INSTOP_WRITE;
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/* Fill fields to update */
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sq_aq->sq.ena = 1;
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sq_aq->sq_mask.ena = 1;
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sq_aq->sq_mask.smq = GENMASK(8, 0);
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sq_aq->sq.smq = otx2_get_smq_idx(pfvf, prio);
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}
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otx2_sync_mbox_msg(&pfvf->mbox);
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if (if_up) {
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if (pfvf->pfc_alloc_status[prio])
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netif_tx_start_all_queues(pfvf->netdev);
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else
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netif_tx_start_queue(netdev_get_tx_queue(dev, prio));
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}
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return 0;
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}
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int otx2_pfc_txschq_update(struct otx2_nic *pfvf)
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{
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bool if_up = netif_running(pfvf->netdev);
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u8 pfc_en = pfvf->pfc_en, pfc_bit_set;
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struct mbox *mbox = &pfvf->mbox;
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int err, prio;
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mutex_lock(&mbox->lock);
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for (prio = 0; prio < NIX_PF_PFC_PRIO_MAX; prio++) {
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pfc_bit_set = pfc_en & (1 << prio);
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/* tx scheduler was created but user wants to disable now */
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if (!pfc_bit_set && pfvf->pfc_alloc_status[prio]) {
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mutex_unlock(&mbox->lock);
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if (if_up)
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netif_tx_stop_all_queues(pfvf->netdev);
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otx2_smq_flush(pfvf, pfvf->pfc_schq_list[NIX_TXSCH_LVL_SMQ][prio]);
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if (if_up)
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netif_tx_start_all_queues(pfvf->netdev);
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/* delete the schq */
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err = otx2_pfc_txschq_stop_one(pfvf, prio);
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if (err) {
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dev_err(pfvf->dev,
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"%s failed to stop PFC tx schedulers for priority: %d\n",
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__func__, prio);
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return err;
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}
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mutex_lock(&mbox->lock);
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goto update_sq_smq_map;
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}
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/* Either PFC bit is not set
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* or Tx scheduler is already mapped for the priority
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*/
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if (!pfc_bit_set || pfvf->pfc_alloc_status[prio])
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continue;
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/* Add new scheduler to the priority */
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err = otx2_pfc_txschq_alloc_one(pfvf, prio);
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if (err) {
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mutex_unlock(&mbox->lock);
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dev_err(pfvf->dev,
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"%s failed to allocate PFC tx schedulers for priority: %d\n",
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__func__, prio);
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return err;
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}
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update_sq_smq_map:
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err = otx2_pfc_update_sq_smq_mapping(pfvf, prio);
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if (err) {
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mutex_unlock(&mbox->lock);
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dev_err(pfvf->dev, "%s failed PFC Tx schq sq:%d mapping", __func__, prio);
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return err;
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}
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}
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err = otx2_pfc_txschq_config(pfvf);
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mutex_unlock(&mbox->lock);
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if (err)
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return err;
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return 0;
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}
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int otx2_pfc_txschq_stop(struct otx2_nic *pfvf)
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{
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u8 pfc_en, pfc_bit_set;
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int prio, err;
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pfc_en = pfvf->pfc_en;
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for (prio = 0; prio < NIX_PF_PFC_PRIO_MAX; prio++) {
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pfc_bit_set = pfc_en & (1 << prio);
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if (!pfc_bit_set || !pfvf->pfc_alloc_status[prio])
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continue;
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/* Delete the existing scheduler */
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err = otx2_pfc_txschq_stop_one(pfvf, prio);
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if (err) {
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dev_err(pfvf->dev, "%s failed to stop PFC TX schedulers\n", __func__);
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return err;
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}
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}
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return 0;
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}
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int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf)
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{
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struct cgx_pfc_cfg *req;
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struct cgx_pfc_rsp *rsp;
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int err = 0;
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if (is_otx2_lbkvf(pfvf->pdev))
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return 0;
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mutex_lock(&pfvf->mbox.lock);
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req = otx2_mbox_alloc_msg_cgx_prio_flow_ctrl_cfg(&pfvf->mbox);
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if (!req) {
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err = -ENOMEM;
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goto unlock;
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}
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if (pfvf->pfc_en) {
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req->rx_pause = true;
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req->tx_pause = true;
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} else {
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req->rx_pause = false;
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req->tx_pause = false;
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}
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req->pfc_en = pfvf->pfc_en;
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if (!otx2_sync_mbox_msg(&pfvf->mbox)) {
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rsp = (struct cgx_pfc_rsp *)
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otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
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if (req->rx_pause != rsp->rx_pause || req->tx_pause != rsp->tx_pause) {
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dev_warn(pfvf->dev,
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"Failed to config PFC\n");
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err = -EPERM;
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}
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}
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unlock:
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mutex_unlock(&pfvf->mbox.lock);
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return err;
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}
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void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx,
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bool pfc_enable)
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{
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bool if_up = netif_running(pfvf->netdev);
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struct npa_aq_enq_req *npa_aq;
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struct nix_aq_enq_req *aq;
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int err = 0;
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if (pfvf->queue_to_pfc_map[qidx] && pfc_enable) {
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dev_warn(pfvf->dev,
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"PFC enable not permitted as Priority %d already mapped to Queue %d\n",
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pfvf->queue_to_pfc_map[qidx], qidx);
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return;
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}
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if (if_up) {
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netif_tx_stop_all_queues(pfvf->netdev);
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netif_carrier_off(pfvf->netdev);
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}
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pfvf->queue_to_pfc_map[qidx] = vlan_prio;
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aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
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if (!aq) {
|
||
|
|
err = -ENOMEM;
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
aq->cq.bpid = pfvf->bpid[vlan_prio];
|
||
|
|
aq->cq_mask.bpid = GENMASK(8, 0);
|
||
|
|
|
||
|
|
/* Fill AQ info */
|
||
|
|
aq->qidx = qidx;
|
||
|
|
aq->ctype = NIX_AQ_CTYPE_CQ;
|
||
|
|
aq->op = NIX_AQ_INSTOP_WRITE;
|
||
|
|
|
||
|
|
otx2_sync_mbox_msg(&pfvf->mbox);
|
||
|
|
|
||
|
|
npa_aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
|
||
|
|
if (!npa_aq) {
|
||
|
|
err = -ENOMEM;
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
npa_aq->aura.nix0_bpid = pfvf->bpid[vlan_prio];
|
||
|
|
npa_aq->aura_mask.nix0_bpid = GENMASK(8, 0);
|
||
|
|
|
||
|
|
/* Fill NPA AQ info */
|
||
|
|
npa_aq->aura_id = qidx;
|
||
|
|
npa_aq->ctype = NPA_AQ_CTYPE_AURA;
|
||
|
|
npa_aq->op = NPA_AQ_INSTOP_WRITE;
|
||
|
|
otx2_sync_mbox_msg(&pfvf->mbox);
|
||
|
|
|
||
|
|
out:
|
||
|
|
if (if_up) {
|
||
|
|
netif_carrier_on(pfvf->netdev);
|
||
|
|
netif_tx_start_all_queues(pfvf->netdev);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (err)
|
||
|
|
dev_warn(pfvf->dev,
|
||
|
|
"Updating BPIDs in CQ and Aura contexts of RQ%d failed with err %d\n",
|
||
|
|
qidx, err);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int otx2_dcbnl_ieee_getpfc(struct net_device *dev, struct ieee_pfc *pfc)
|
||
|
|
{
|
||
|
|
struct otx2_nic *pfvf = netdev_priv(dev);
|
||
|
|
|
||
|
|
pfc->pfc_cap = IEEE_8021QAZ_MAX_TCS;
|
||
|
|
pfc->pfc_en = pfvf->pfc_en;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int otx2_dcbnl_ieee_setpfc(struct net_device *dev, struct ieee_pfc *pfc)
|
||
|
|
{
|
||
|
|
struct otx2_nic *pfvf = netdev_priv(dev);
|
||
|
|
int err;
|
||
|
|
|
||
|
|
/* Save PFC configuration to interface */
|
||
|
|
pfvf->pfc_en = pfc->pfc_en;
|
||
|
|
|
||
|
|
if (pfvf->hw.tx_queues >= NIX_PF_PFC_PRIO_MAX)
|
||
|
|
goto process_pfc;
|
||
|
|
|
||
|
|
/* Check if the PFC configuration can be
|
||
|
|
* supported by the tx queue configuration
|
||
|
|
*/
|
||
|
|
err = otx2_check_pfc_config(pfvf);
|
||
|
|
if (err)
|
||
|
|
return err;
|
||
|
|
|
||
|
|
process_pfc:
|
||
|
|
err = otx2_config_priority_flow_ctrl(pfvf);
|
||
|
|
if (err)
|
||
|
|
return err;
|
||
|
|
|
||
|
|
/* Request Per channel Bpids */
|
||
|
|
if (pfc->pfc_en)
|
||
|
|
otx2_nix_config_bp(pfvf, true);
|
||
|
|
|
||
|
|
err = otx2_pfc_txschq_update(pfvf);
|
||
|
|
if (err) {
|
||
|
|
dev_err(pfvf->dev, "%s failed to update TX schedulers\n", __func__);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static u8 otx2_dcbnl_getdcbx(struct net_device __always_unused *dev)
|
||
|
|
{
|
||
|
|
return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
|
||
|
|
}
|
||
|
|
|
||
|
|
static u8 otx2_dcbnl_setdcbx(struct net_device __always_unused *dev, u8 mode)
|
||
|
|
{
|
||
|
|
return (mode != (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE)) ? 1 : 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct dcbnl_rtnl_ops otx2_dcbnl_ops = {
|
||
|
|
.ieee_getpfc = otx2_dcbnl_ieee_getpfc,
|
||
|
|
.ieee_setpfc = otx2_dcbnl_ieee_setpfc,
|
||
|
|
.getdcbx = otx2_dcbnl_getdcbx,
|
||
|
|
.setdcbx = otx2_dcbnl_setdcbx,
|
||
|
|
};
|
||
|
|
|
||
|
|
int otx2_dcbnl_set_ops(struct net_device *dev)
|
||
|
|
{
|
||
|
|
struct otx2_nic *pfvf = netdev_priv(dev);
|
||
|
|
|
||
|
|
pfvf->queue_to_pfc_map = devm_kzalloc(pfvf->dev, pfvf->hw.rx_queues,
|
||
|
|
GFP_KERNEL);
|
||
|
|
if (!pfvf->queue_to_pfc_map)
|
||
|
|
return -ENOMEM;
|
||
|
|
dev->dcbnl_ops = &otx2_dcbnl_ops;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|