360 lines
9.3 KiB
C
360 lines
9.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/* Microchip Sparx5 Switch driver
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*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*/
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#include "sparx5_main_regs.h"
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#include "sparx5_main.h"
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#define XTR_EOF_0 ntohl((__force __be32)0x80000000u)
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#define XTR_EOF_1 ntohl((__force __be32)0x80000001u)
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#define XTR_EOF_2 ntohl((__force __be32)0x80000002u)
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#define XTR_EOF_3 ntohl((__force __be32)0x80000003u)
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#define XTR_PRUNED ntohl((__force __be32)0x80000004u)
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#define XTR_ABORT ntohl((__force __be32)0x80000005u)
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#define XTR_ESCAPE ntohl((__force __be32)0x80000006u)
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#define XTR_NOT_READY ntohl((__force __be32)0x80000007u)
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#define XTR_VALID_BYTES(x) (4 - ((x) & 3))
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#define INJ_TIMEOUT_NS 50000
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void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp)
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{
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/* Start flush */
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spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH);
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/* Allow to drain */
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mdelay(1);
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/* All Queues normal */
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spx5_wr(0, sparx5, QS_XTR_FLUSH);
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}
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void sparx5_ifh_parse(u32 *ifh, struct frame_info *info)
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{
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u8 *xtr_hdr = (u8 *)ifh;
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/* FWD is bit 45-72 (28 bits), but we only read the 27 LSB for now */
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u32 fwd =
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((u32)xtr_hdr[27] << 24) |
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((u32)xtr_hdr[28] << 16) |
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((u32)xtr_hdr[29] << 8) |
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((u32)xtr_hdr[30] << 0);
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fwd = (fwd >> 5);
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info->src_port = FIELD_GET(GENMASK(7, 1), fwd);
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info->timestamp =
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((u64)xtr_hdr[2] << 24) |
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((u64)xtr_hdr[3] << 16) |
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((u64)xtr_hdr[4] << 8) |
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((u64)xtr_hdr[5] << 0);
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}
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static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp, bool byte_swap)
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{
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bool eof_flag = false, pruned_flag = false, abort_flag = false;
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struct net_device *netdev;
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struct sparx5_port *port;
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struct frame_info fi;
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int i, byte_cnt = 0;
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struct sk_buff *skb;
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u32 ifh[IFH_LEN];
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u32 *rxbuf;
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/* Get IFH */
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for (i = 0; i < IFH_LEN; i++)
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ifh[i] = spx5_rd(sparx5, QS_XTR_RD(grp));
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/* Decode IFH (whats needed) */
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sparx5_ifh_parse(ifh, &fi);
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/* Map to port netdev */
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port = fi.src_port < SPX5_PORTS ?
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sparx5->ports[fi.src_port] : NULL;
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if (!port || !port->ndev) {
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dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port);
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sparx5_xtr_flush(sparx5, grp);
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return;
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}
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/* Have netdev, get skb */
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netdev = port->ndev;
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skb = netdev_alloc_skb(netdev, netdev->mtu + ETH_HLEN);
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if (!skb) {
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sparx5_xtr_flush(sparx5, grp);
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dev_err(sparx5->dev, "No skb allocated\n");
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netdev->stats.rx_dropped++;
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return;
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}
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rxbuf = (u32 *)skb->data;
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/* Now, pull frame data */
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while (!eof_flag) {
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u32 val = spx5_rd(sparx5, QS_XTR_RD(grp));
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u32 cmp = val;
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if (byte_swap)
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cmp = ntohl((__force __be32)val);
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switch (cmp) {
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case XTR_NOT_READY:
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break;
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case XTR_ABORT:
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/* No accompanying data */
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abort_flag = true;
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eof_flag = true;
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break;
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case XTR_EOF_0:
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case XTR_EOF_1:
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case XTR_EOF_2:
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case XTR_EOF_3:
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/* This assumes STATUS_WORD_POS == 1, Status
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* just after last data
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*/
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if (!byte_swap)
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val = ntohl((__force __be32)val);
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byte_cnt -= (4 - XTR_VALID_BYTES(val));
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eof_flag = true;
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break;
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case XTR_PRUNED:
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/* But get the last 4 bytes as well */
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eof_flag = true;
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pruned_flag = true;
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fallthrough;
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case XTR_ESCAPE:
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*rxbuf = spx5_rd(sparx5, QS_XTR_RD(grp));
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byte_cnt += 4;
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rxbuf++;
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break;
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default:
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*rxbuf = val;
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byte_cnt += 4;
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rxbuf++;
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}
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}
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if (abort_flag || pruned_flag || !eof_flag) {
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netdev_err(netdev, "Discarded frame: abort:%d pruned:%d eof:%d\n",
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abort_flag, pruned_flag, eof_flag);
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kfree_skb(skb);
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netdev->stats.rx_dropped++;
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return;
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}
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/* Everything we see on an interface that is in the HW bridge
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* has already been forwarded
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*/
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if (test_bit(port->portno, sparx5->bridge_mask))
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skb->offload_fwd_mark = 1;
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/* Finish up skb */
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skb_put(skb, byte_cnt - ETH_FCS_LEN);
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eth_skb_pad(skb);
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sparx5_ptp_rxtstamp(sparx5, skb, fi.timestamp);
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skb->protocol = eth_type_trans(skb, netdev);
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netdev->stats.rx_bytes += skb->len;
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netdev->stats.rx_packets++;
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netif_rx(skb);
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}
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static int sparx5_inject(struct sparx5 *sparx5,
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u32 *ifh,
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struct sk_buff *skb,
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struct net_device *ndev)
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{
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int grp = INJ_QUEUE;
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u32 val, w, count;
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u8 *buf;
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val = spx5_rd(sparx5, QS_INJ_STATUS);
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if (!(QS_INJ_STATUS_FIFO_RDY_GET(val) & BIT(grp))) {
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pr_err_ratelimited("Injection: Queue not ready: 0x%lx\n",
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QS_INJ_STATUS_FIFO_RDY_GET(val));
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return -EBUSY;
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}
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/* Indicate SOF */
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spx5_wr(QS_INJ_CTRL_SOF_SET(1) |
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QS_INJ_CTRL_GAP_SIZE_SET(1),
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sparx5, QS_INJ_CTRL(grp));
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/* Write the IFH to the chip. */
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for (w = 0; w < IFH_LEN; w++)
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spx5_wr(ifh[w], sparx5, QS_INJ_WR(grp));
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/* Write words, round up */
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count = DIV_ROUND_UP(skb->len, 4);
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buf = skb->data;
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for (w = 0; w < count; w++, buf += 4) {
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val = get_unaligned((const u32 *)buf);
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spx5_wr(val, sparx5, QS_INJ_WR(grp));
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}
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/* Add padding */
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while (w < (60 / 4)) {
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spx5_wr(0, sparx5, QS_INJ_WR(grp));
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w++;
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}
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/* Indicate EOF and valid bytes in last word */
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spx5_wr(QS_INJ_CTRL_GAP_SIZE_SET(1) |
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QS_INJ_CTRL_VLD_BYTES_SET(skb->len < 60 ? 0 : skb->len % 4) |
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QS_INJ_CTRL_EOF_SET(1),
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sparx5, QS_INJ_CTRL(grp));
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/* Add dummy CRC */
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spx5_wr(0, sparx5, QS_INJ_WR(grp));
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w++;
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val = spx5_rd(sparx5, QS_INJ_STATUS);
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if (QS_INJ_STATUS_WMARK_REACHED_GET(val) & BIT(grp)) {
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struct sparx5_port *port = netdev_priv(ndev);
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pr_err_ratelimited("Injection: Watermark reached: 0x%lx\n",
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QS_INJ_STATUS_WMARK_REACHED_GET(val));
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netif_stop_queue(ndev);
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hrtimer_start(&port->inj_timer, INJ_TIMEOUT_NS,
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HRTIMER_MODE_REL);
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}
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return NETDEV_TX_OK;
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}
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netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev)
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{
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struct net_device_stats *stats = &dev->stats;
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struct sparx5_port *port = netdev_priv(dev);
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struct sparx5 *sparx5 = port->sparx5;
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u32 ifh[IFH_LEN];
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netdev_tx_t ret;
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memset(ifh, 0, IFH_LEN * 4);
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sparx5_set_port_ifh(ifh, port->portno);
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if (sparx5->ptp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
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if (sparx5_ptp_txtstamp_request(port, skb) < 0)
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return NETDEV_TX_BUSY;
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sparx5_set_port_ifh_rew_op(ifh, SPARX5_SKB_CB(skb)->rew_op);
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sparx5_set_port_ifh_pdu_type(ifh, SPARX5_SKB_CB(skb)->pdu_type);
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sparx5_set_port_ifh_pdu_w16_offset(ifh, SPARX5_SKB_CB(skb)->pdu_w16_offset);
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sparx5_set_port_ifh_timestamp(ifh, SPARX5_SKB_CB(skb)->ts_id);
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}
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skb_tx_timestamp(skb);
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if (sparx5->fdma_irq > 0)
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ret = sparx5_fdma_xmit(sparx5, ifh, skb);
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else
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ret = sparx5_inject(sparx5, ifh, skb, dev);
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if (ret == -EBUSY)
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goto busy;
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if (ret < 0)
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goto drop;
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stats->tx_bytes += skb->len;
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stats->tx_packets++;
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sparx5->tx.packets++;
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if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
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SPARX5_SKB_CB(skb)->rew_op == IFH_REW_OP_TWO_STEP_PTP)
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return NETDEV_TX_OK;
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dev_consume_skb_any(skb);
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return NETDEV_TX_OK;
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drop:
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stats->tx_dropped++;
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sparx5->tx.dropped++;
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dev_kfree_skb_any(skb);
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return NETDEV_TX_OK;
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busy:
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if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
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SPARX5_SKB_CB(skb)->rew_op == IFH_REW_OP_TWO_STEP_PTP)
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sparx5_ptp_txtstamp_release(port, skb);
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return NETDEV_TX_BUSY;
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}
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static enum hrtimer_restart sparx5_injection_timeout(struct hrtimer *tmr)
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{
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struct sparx5_port *port = container_of(tmr, struct sparx5_port,
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inj_timer);
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int grp = INJ_QUEUE;
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u32 val;
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val = spx5_rd(port->sparx5, QS_INJ_STATUS);
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if (QS_INJ_STATUS_WMARK_REACHED_GET(val) & BIT(grp)) {
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pr_err_ratelimited("Injection: Reset watermark count\n");
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/* Reset Watermark count to restart */
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spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1),
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DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR,
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port->sparx5,
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DSM_DEV_TX_STOP_WM_CFG(port->portno));
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}
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netif_wake_queue(port->ndev);
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return HRTIMER_NORESTART;
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}
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int sparx5_manual_injection_mode(struct sparx5 *sparx5)
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{
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const int byte_swap = 1;
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int portno;
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/* Change mode to manual extraction and injection */
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spx5_wr(QS_XTR_GRP_CFG_MODE_SET(1) |
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QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(1) |
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QS_XTR_GRP_CFG_BYTE_SWAP_SET(byte_swap),
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sparx5, QS_XTR_GRP_CFG(XTR_QUEUE));
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spx5_wr(QS_INJ_GRP_CFG_MODE_SET(1) |
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QS_INJ_GRP_CFG_BYTE_SWAP_SET(byte_swap),
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sparx5, QS_INJ_GRP_CFG(INJ_QUEUE));
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/* CPU ports capture setup */
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for (portno = SPX5_PORT_CPU_0; portno <= SPX5_PORT_CPU_1; portno++) {
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/* ASM CPU port: No preamble, IFH, enable padding */
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spx5_wr(ASM_PORT_CFG_PAD_ENA_SET(1) |
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ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(1) |
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ASM_PORT_CFG_INJ_FORMAT_CFG_SET(1), /* 1 = IFH */
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sparx5, ASM_PORT_CFG(portno));
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/* Reset WM cnt to unclog queued frames */
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spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1),
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DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR,
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sparx5,
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DSM_DEV_TX_STOP_WM_CFG(portno));
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/* Set Disassembler Stop Watermark level */
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spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(0),
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DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM,
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sparx5,
|
||
|
|
DSM_DEV_TX_STOP_WM_CFG(portno));
|
||
|
|
|
||
|
|
/* Enable Disassembler buffer underrun watchdog
|
||
|
|
*/
|
||
|
|
spx5_rmw(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(0),
|
||
|
|
DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS,
|
||
|
|
sparx5,
|
||
|
|
DSM_BUF_CFG(portno));
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
irqreturn_t sparx5_xtr_handler(int irq, void *_sparx5)
|
||
|
|
{
|
||
|
|
struct sparx5 *s5 = _sparx5;
|
||
|
|
int poll = 64;
|
||
|
|
|
||
|
|
/* Check data in queue */
|
||
|
|
while (spx5_rd(s5, QS_XTR_DATA_PRESENT) & BIT(XTR_QUEUE) && poll-- > 0)
|
||
|
|
sparx5_xtr_grp(s5, XTR_QUEUE, false);
|
||
|
|
|
||
|
|
return IRQ_HANDLED;
|
||
|
|
}
|
||
|
|
|
||
|
|
void sparx5_port_inj_timer_setup(struct sparx5_port *port)
|
||
|
|
{
|
||
|
|
hrtimer_init(&port->inj_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
|
||
|
|
port->inj_timer.function = sparx5_injection_timeout;
|
||
|
|
}
|