239 lines
6.2 KiB
C
239 lines
6.2 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/* Microchip Sparx5 Switch driver
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*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*/
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#include "sparx5_main_regs.h"
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#include "sparx5_main.h"
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static int sparx5_vlant_set_mask(struct sparx5 *sparx5, u16 vid)
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{
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u32 mask[3];
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/* Divide up mask in 32 bit words */
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bitmap_to_arr32(mask, sparx5->vlan_mask[vid], SPX5_PORTS);
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/* Output mask to respective registers */
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spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid));
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spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid));
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spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid));
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return 0;
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}
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void sparx5_vlan_init(struct sparx5 *sparx5)
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{
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u16 vid;
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spx5_rmw(ANA_L3_VLAN_CTRL_VLAN_ENA_SET(1),
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ANA_L3_VLAN_CTRL_VLAN_ENA,
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sparx5,
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ANA_L3_VLAN_CTRL);
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/* Map VLAN = FID */
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for (vid = NULL_VID; vid < VLAN_N_VID; vid++)
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spx5_rmw(ANA_L3_VLAN_CFG_VLAN_FID_SET(vid),
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ANA_L3_VLAN_CFG_VLAN_FID,
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sparx5,
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ANA_L3_VLAN_CFG(vid));
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}
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void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno)
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{
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struct sparx5_port *port = sparx5->ports[portno];
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/* Configure PVID */
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spx5_rmw(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(0) |
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ANA_CL_VLAN_CTRL_PORT_VID_SET(port->pvid),
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ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA |
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ANA_CL_VLAN_CTRL_PORT_VID,
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sparx5,
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ANA_CL_VLAN_CTRL(port->portno));
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}
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int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid,
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bool untagged)
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{
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struct sparx5 *sparx5 = port->sparx5;
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int ret;
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/* Untagged egress vlan classification */
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if (untagged && port->vid != vid) {
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if (port->vid) {
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netdev_err(port->ndev,
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"Port already has a native VLAN: %d\n",
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port->vid);
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return -EBUSY;
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}
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port->vid = vid;
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}
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/* Make the port a member of the VLAN */
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set_bit(port->portno, sparx5->vlan_mask[vid]);
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ret = sparx5_vlant_set_mask(sparx5, vid);
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if (ret)
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return ret;
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/* Default ingress vlan classification */
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if (pvid)
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port->pvid = vid;
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sparx5_vlan_port_apply(sparx5, port);
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return 0;
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}
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int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid)
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{
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struct sparx5 *sparx5 = port->sparx5;
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int ret;
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/* 8021q removes VID 0 on module unload for all interfaces
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* with VLAN filtering feature. We need to keep it to receive
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* untagged traffic.
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*/
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if (vid == 0)
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return 0;
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/* Stop the port from being a member of the vlan */
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clear_bit(port->portno, sparx5->vlan_mask[vid]);
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ret = sparx5_vlant_set_mask(sparx5, vid);
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if (ret)
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return ret;
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/* Ingress */
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if (port->pvid == vid)
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port->pvid = 0;
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/* Egress */
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if (port->vid == vid)
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port->vid = 0;
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sparx5_vlan_port_apply(sparx5, port);
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return 0;
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}
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void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable)
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{
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struct sparx5 *sparx5 = port->sparx5;
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u32 val, mask;
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/* mask is spread across 3 registers x 32 bit */
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if (port->portno < 32) {
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mask = BIT(port->portno);
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val = enable ? mask : 0;
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spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG(pgid));
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} else if (port->portno < 64) {
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mask = BIT(port->portno - 32);
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val = enable ? mask : 0;
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spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG1(pgid));
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} else if (port->portno < SPX5_PORTS) {
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mask = BIT(port->portno - 64);
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val = enable ? mask : 0;
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spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG2(pgid));
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} else {
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netdev_err(port->ndev, "Invalid port no: %d\n", port->portno);
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}
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}
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void sparx5_pgid_clear(struct sparx5 *spx5, int pgid)
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{
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spx5_wr(0, spx5, ANA_AC_PGID_CFG(pgid));
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spx5_wr(0, spx5, ANA_AC_PGID_CFG1(pgid));
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spx5_wr(0, spx5, ANA_AC_PGID_CFG2(pgid));
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}
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void sparx5_pgid_read_mask(struct sparx5 *spx5, int pgid, u32 portmask[3])
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{
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portmask[0] = spx5_rd(spx5, ANA_AC_PGID_CFG(pgid));
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portmask[1] = spx5_rd(spx5, ANA_AC_PGID_CFG1(pgid));
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portmask[2] = spx5_rd(spx5, ANA_AC_PGID_CFG2(pgid));
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}
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void sparx5_update_fwd(struct sparx5 *sparx5)
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{
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DECLARE_BITMAP(workmask, SPX5_PORTS);
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u32 mask[3];
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int port;
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/* Divide up fwd mask in 32 bit words */
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bitmap_to_arr32(mask, sparx5->bridge_fwd_mask, SPX5_PORTS);
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/* Update flood masks */
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for (port = PGID_UC_FLOOD; port <= PGID_BCAST; port++) {
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spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port));
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spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port));
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spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port));
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}
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/* Update SRC masks */
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for (port = 0; port < SPX5_PORTS; port++) {
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if (test_bit(port, sparx5->bridge_fwd_mask)) {
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/* Allow to send to all bridged but self */
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bitmap_copy(workmask, sparx5->bridge_fwd_mask, SPX5_PORTS);
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clear_bit(port, workmask);
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bitmap_to_arr32(mask, workmask, SPX5_PORTS);
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spx5_wr(mask[0], sparx5, ANA_AC_SRC_CFG(port));
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spx5_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port));
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spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port));
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} else {
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spx5_wr(0, sparx5, ANA_AC_SRC_CFG(port));
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spx5_wr(0, sparx5, ANA_AC_SRC_CFG1(port));
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spx5_wr(0, sparx5, ANA_AC_SRC_CFG2(port));
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}
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}
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/* Learning enabled only for bridged ports */
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bitmap_and(workmask, sparx5->bridge_fwd_mask,
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sparx5->bridge_lrn_mask, SPX5_PORTS);
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bitmap_to_arr32(mask, workmask, SPX5_PORTS);
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/* Apply learning mask */
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spx5_wr(mask[0], sparx5, ANA_L2_AUTO_LRN_CFG);
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spx5_wr(mask[1], sparx5, ANA_L2_AUTO_LRN_CFG1);
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spx5_wr(mask[2], sparx5, ANA_L2_AUTO_LRN_CFG2);
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}
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void sparx5_vlan_port_apply(struct sparx5 *sparx5,
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struct sparx5_port *port)
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{
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u32 val;
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/* Configure PVID, vlan aware */
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val = ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(port->vlan_aware) |
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ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(port->vlan_aware) |
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ANA_CL_VLAN_CTRL_PORT_VID_SET(port->pvid);
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spx5_wr(val, sparx5, ANA_CL_VLAN_CTRL(port->portno));
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val = 0;
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if (port->vlan_aware && !port->pvid)
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/* If port is vlan-aware and tagged, drop untagged and
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* priority tagged frames.
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*/
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val = ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(1) |
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ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(1) |
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ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(1);
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spx5_wr(val, sparx5,
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ANA_CL_VLAN_FILTER_CTRL(port->portno, 0));
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/* Egress configuration (REW_TAG_CFG): VLAN tag selected via IFH */
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val = REW_TAG_CTRL_TAG_TPID_CFG_SET(5);
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if (port->vlan_aware) {
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if (port->vid)
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/* Tag all frames except when VID == DEFAULT_VLAN */
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val |= REW_TAG_CTRL_TAG_CFG_SET(1);
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else
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val |= REW_TAG_CTRL_TAG_CFG_SET(3);
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}
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spx5_wr(val, sparx5, REW_TAG_CTRL(port->portno));
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/* Egress VID */
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spx5_rmw(REW_PORT_VLAN_CFG_PORT_VID_SET(port->vid),
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REW_PORT_VLAN_CFG_PORT_VID,
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sparx5,
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REW_PORT_VLAN_CFG(port->portno));
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}
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