401 lines
11 KiB
C
401 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* dwmac-ingenic.c - Ingenic SoCs DWMAC specific glue layer
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*
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* Copyright (c) 2021 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_net.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/stmmac.h>
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#include "stmmac_platform.h"
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#define MACPHYC_TXCLK_SEL_MASK GENMASK(31, 31)
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#define MACPHYC_TXCLK_SEL_OUTPUT 0x1
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#define MACPHYC_TXCLK_SEL_INPUT 0x0
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#define MACPHYC_MODE_SEL_MASK GENMASK(31, 31)
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#define MACPHYC_MODE_SEL_RMII 0x0
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#define MACPHYC_TX_SEL_MASK GENMASK(19, 19)
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#define MACPHYC_TX_SEL_ORIGIN 0x0
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#define MACPHYC_TX_SEL_DELAY 0x1
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#define MACPHYC_TX_DELAY_MASK GENMASK(18, 12)
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#define MACPHYC_RX_SEL_MASK GENMASK(11, 11)
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#define MACPHYC_RX_SEL_ORIGIN 0x0
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#define MACPHYC_RX_SEL_DELAY 0x1
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#define MACPHYC_RX_DELAY_MASK GENMASK(10, 4)
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#define MACPHYC_SOFT_RST_MASK GENMASK(3, 3)
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#define MACPHYC_PHY_INFT_MASK GENMASK(2, 0)
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#define MACPHYC_PHY_INFT_RMII 0x4
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#define MACPHYC_PHY_INFT_RGMII 0x1
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#define MACPHYC_PHY_INFT_GMII 0x0
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#define MACPHYC_PHY_INFT_MII 0x0
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#define MACPHYC_TX_DELAY_PS_MAX 2496
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#define MACPHYC_TX_DELAY_PS_MIN 20
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#define MACPHYC_RX_DELAY_PS_MAX 2496
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#define MACPHYC_RX_DELAY_PS_MIN 20
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enum ingenic_mac_version {
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ID_JZ4775,
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ID_X1000,
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ID_X1600,
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ID_X1830,
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ID_X2000,
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};
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struct ingenic_mac {
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const struct ingenic_soc_info *soc_info;
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struct device *dev;
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struct regmap *regmap;
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int rx_delay;
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int tx_delay;
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};
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struct ingenic_soc_info {
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enum ingenic_mac_version version;
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u32 mask;
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int (*set_mode)(struct plat_stmmacenet_data *plat_dat);
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};
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static int ingenic_mac_init(struct plat_stmmacenet_data *plat_dat)
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{
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struct ingenic_mac *mac = plat_dat->bsp_priv;
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int ret;
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if (mac->soc_info->set_mode) {
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ret = mac->soc_info->set_mode(plat_dat);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int jz4775_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
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{
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struct ingenic_mac *mac = plat_dat->bsp_priv;
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unsigned int val;
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switch (plat_dat->interface) {
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case PHY_INTERFACE_MODE_MII:
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val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
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FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_MII);
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dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_MII\n");
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break;
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case PHY_INTERFACE_MODE_GMII:
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val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
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FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_GMII);
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dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_GMII\n");
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break;
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case PHY_INTERFACE_MODE_RMII:
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val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
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FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);
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dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
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FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RGMII);
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dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RGMII\n");
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break;
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default:
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dev_err(mac->dev, "Unsupported interface %d", plat_dat->interface);
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return -EINVAL;
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}
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/* Update MAC PHY control register */
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return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
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}
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static int x1000_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
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{
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struct ingenic_mac *mac = plat_dat->bsp_priv;
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switch (plat_dat->interface) {
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case PHY_INTERFACE_MODE_RMII:
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dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
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break;
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default:
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dev_err(mac->dev, "Unsupported interface %d", plat_dat->interface);
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return -EINVAL;
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}
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/* Update MAC PHY control register */
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return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, 0);
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}
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static int x1600_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
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{
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struct ingenic_mac *mac = plat_dat->bsp_priv;
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unsigned int val;
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switch (plat_dat->interface) {
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case PHY_INTERFACE_MODE_RMII:
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val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);
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dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
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break;
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default:
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dev_err(mac->dev, "Unsupported interface %d", plat_dat->interface);
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return -EINVAL;
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}
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/* Update MAC PHY control register */
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return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
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}
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static int x1830_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
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{
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struct ingenic_mac *mac = plat_dat->bsp_priv;
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unsigned int val;
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switch (plat_dat->interface) {
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case PHY_INTERFACE_MODE_RMII:
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val = FIELD_PREP(MACPHYC_MODE_SEL_MASK, MACPHYC_MODE_SEL_RMII) |
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FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);
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dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
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break;
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default:
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dev_err(mac->dev, "Unsupported interface %d", plat_dat->interface);
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return -EINVAL;
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}
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/* Update MAC PHY control register */
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return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
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}
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static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
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{
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struct ingenic_mac *mac = plat_dat->bsp_priv;
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unsigned int val;
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switch (plat_dat->interface) {
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case PHY_INTERFACE_MODE_RMII:
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val = FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |
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FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN) |
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FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);
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dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RGMII);
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if (mac->tx_delay == 0)
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val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN);
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else
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val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_DELAY) |
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FIELD_PREP(MACPHYC_TX_DELAY_MASK, (mac->tx_delay + 9750) / 19500 - 1);
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if (mac->rx_delay == 0)
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val |= FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);
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else
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val |= FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_DELAY) |
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FIELD_PREP(MACPHYC_RX_DELAY_MASK, (mac->rx_delay + 9750) / 19500 - 1);
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dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RGMII\n");
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break;
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default:
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dev_err(mac->dev, "Unsupported interface %d", plat_dat->interface);
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return -EINVAL;
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}
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/* Update MAC PHY control register */
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return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
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}
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static int ingenic_mac_probe(struct platform_device *pdev)
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{
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struct plat_stmmacenet_data *plat_dat;
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struct stmmac_resources stmmac_res;
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struct ingenic_mac *mac;
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const struct ingenic_soc_info *data;
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u32 tx_delay_ps, rx_delay_ps;
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int ret;
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ret = stmmac_get_platform_resources(pdev, &stmmac_res);
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if (ret)
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return ret;
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plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
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if (IS_ERR(plat_dat))
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return PTR_ERR(plat_dat);
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mac = devm_kzalloc(&pdev->dev, sizeof(*mac), GFP_KERNEL);
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if (!mac) {
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ret = -ENOMEM;
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goto err_remove_config_dt;
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}
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data = of_device_get_match_data(&pdev->dev);
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if (!data) {
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dev_err(&pdev->dev, "No of match data provided\n");
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ret = -EINVAL;
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goto err_remove_config_dt;
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}
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/* Get MAC PHY control register */
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mac->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "mode-reg");
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if (IS_ERR(mac->regmap)) {
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dev_err(&pdev->dev, "%s: Failed to get syscon regmap\n", __func__);
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ret = PTR_ERR(mac->regmap);
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goto err_remove_config_dt;
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}
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if (!of_property_read_u32(pdev->dev.of_node, "tx-clk-delay-ps", &tx_delay_ps)) {
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if (tx_delay_ps >= MACPHYC_TX_DELAY_PS_MIN &&
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tx_delay_ps <= MACPHYC_TX_DELAY_PS_MAX) {
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mac->tx_delay = tx_delay_ps * 1000;
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} else {
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dev_err(&pdev->dev, "Invalid TX clock delay: %dps\n", tx_delay_ps);
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ret = -EINVAL;
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goto err_remove_config_dt;
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}
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}
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if (!of_property_read_u32(pdev->dev.of_node, "rx-clk-delay-ps", &rx_delay_ps)) {
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if (rx_delay_ps >= MACPHYC_RX_DELAY_PS_MIN &&
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rx_delay_ps <= MACPHYC_RX_DELAY_PS_MAX) {
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mac->rx_delay = rx_delay_ps * 1000;
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} else {
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dev_err(&pdev->dev, "Invalid RX clock delay: %dps\n", rx_delay_ps);
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ret = -EINVAL;
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goto err_remove_config_dt;
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}
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}
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mac->soc_info = data;
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mac->dev = &pdev->dev;
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plat_dat->bsp_priv = mac;
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ret = ingenic_mac_init(plat_dat);
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if (ret)
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goto err_remove_config_dt;
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ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
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if (ret)
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goto err_remove_config_dt;
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return 0;
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err_remove_config_dt:
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stmmac_remove_config_dt(pdev, plat_dat);
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return ret;
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}
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#ifdef CONFIG_PM_SLEEP
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static int ingenic_mac_suspend(struct device *dev)
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{
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int ret;
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ret = stmmac_suspend(dev);
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return ret;
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}
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static int ingenic_mac_resume(struct device *dev)
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{
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struct net_device *ndev = dev_get_drvdata(dev);
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struct stmmac_priv *priv = netdev_priv(ndev);
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int ret;
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ret = ingenic_mac_init(priv->plat);
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if (ret)
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return ret;
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ret = stmmac_resume(dev);
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return ret;
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}
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#endif /* CONFIG_PM_SLEEP */
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static SIMPLE_DEV_PM_OPS(ingenic_mac_pm_ops, ingenic_mac_suspend, ingenic_mac_resume);
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static struct ingenic_soc_info jz4775_soc_info = {
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.version = ID_JZ4775,
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.mask = MACPHYC_TXCLK_SEL_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,
|
||
|
|
|
||
|
|
.set_mode = jz4775_mac_set_mode,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct ingenic_soc_info x1000_soc_info = {
|
||
|
|
.version = ID_X1000,
|
||
|
|
.mask = MACPHYC_SOFT_RST_MASK,
|
||
|
|
|
||
|
|
.set_mode = x1000_mac_set_mode,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct ingenic_soc_info x1600_soc_info = {
|
||
|
|
.version = ID_X1600,
|
||
|
|
.mask = MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,
|
||
|
|
|
||
|
|
.set_mode = x1600_mac_set_mode,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct ingenic_soc_info x1830_soc_info = {
|
||
|
|
.version = ID_X1830,
|
||
|
|
.mask = MACPHYC_MODE_SEL_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,
|
||
|
|
|
||
|
|
.set_mode = x1830_mac_set_mode,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct ingenic_soc_info x2000_soc_info = {
|
||
|
|
.version = ID_X2000,
|
||
|
|
.mask = MACPHYC_TX_SEL_MASK | MACPHYC_TX_DELAY_MASK | MACPHYC_RX_SEL_MASK |
|
||
|
|
MACPHYC_RX_DELAY_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,
|
||
|
|
|
||
|
|
.set_mode = x2000_mac_set_mode,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id ingenic_mac_of_matches[] = {
|
||
|
|
{ .compatible = "ingenic,jz4775-mac", .data = &jz4775_soc_info },
|
||
|
|
{ .compatible = "ingenic,x1000-mac", .data = &x1000_soc_info },
|
||
|
|
{ .compatible = "ingenic,x1600-mac", .data = &x1600_soc_info },
|
||
|
|
{ .compatible = "ingenic,x1830-mac", .data = &x1830_soc_info },
|
||
|
|
{ .compatible = "ingenic,x2000-mac", .data = &x2000_soc_info },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, ingenic_mac_of_matches);
|
||
|
|
|
||
|
|
static struct platform_driver ingenic_mac_driver = {
|
||
|
|
.probe = ingenic_mac_probe,
|
||
|
|
.remove = stmmac_pltfr_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "ingenic-mac",
|
||
|
|
.pm = pm_ptr(&ingenic_mac_pm_ops),
|
||
|
|
.of_match_table = ingenic_mac_of_matches,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
module_platform_driver(ingenic_mac_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>");
|
||
|
|
MODULE_DESCRIPTION("Ingenic SoCs DWMAC specific glue layer");
|
||
|
|
MODULE_LICENSE("GPL v2");
|