271 lines
7.5 KiB
C
271 lines
7.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/******************************************************************************
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*
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* (C)Copyright 1998,1999 SysKonnect,
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* a business unit of Schneider & Koch & Co. Datensysteme GmbH.
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*
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* The information in this file is provided "AS IS" without warranty.
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*
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******************************************************************************/
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/*
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* AMD Fplus in tag mode data structs
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* defs for fplustm.c
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*/
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#ifndef _FPLUS_
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#define _FPLUS_
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#ifndef HW_PTR
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#define HW_PTR void __iomem *
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#endif
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/*
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* fplus error statistic structure
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*/
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struct err_st {
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u_long err_valid ; /* memory status valid */
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u_long err_abort ; /* memory status receive abort */
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u_long err_e_indicator ; /* error indicator */
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u_long err_crc ; /* error detected (CRC or length) */
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u_long err_llc_frame ; /* LLC frame */
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u_long err_mac_frame ; /* MAC frame */
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u_long err_smt_frame ; /* SMT frame */
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u_long err_imp_frame ; /* implementer frame */
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u_long err_no_buf ; /* no buffer available */
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u_long err_too_long ; /* longer than max. buffer */
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u_long err_bec_stat ; /* beacon state entered */
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u_long err_clm_stat ; /* claim state entered */
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u_long err_sifg_det ; /* short interframe gap detect */
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u_long err_phinv ; /* PHY invalid */
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u_long err_tkiss ; /* token issued */
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u_long err_tkerr ; /* token error */
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} ;
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/*
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* Transmit Descriptor struct
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*/
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struct s_smt_fp_txd {
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__le32 txd_tbctrl ; /* transmit buffer control */
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__le32 txd_txdscr ; /* transmit frame status word */
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__le32 txd_tbadr ; /* physical tx buffer address */
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__le32 txd_ntdadr ; /* physical pointer to the next TxD */
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#ifdef ENA_64BIT_SUP
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__le32 txd_tbadr_hi ; /* physical tx buffer addr (high dword)*/
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#endif
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char far *txd_virt ; /* virtual pointer to the data frag */
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/* virt pointer to the next TxD */
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struct s_smt_fp_txd volatile far *txd_next ;
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struct s_txd_os txd_os ; /* OS - specific struct */
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} ;
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/*
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* Receive Descriptor struct
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*/
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struct s_smt_fp_rxd {
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__le32 rxd_rbctrl ; /* receive buffer control */
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__le32 rxd_rfsw ; /* receive frame status word */
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__le32 rxd_rbadr ; /* physical rx buffer address */
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__le32 rxd_nrdadr ; /* physical pointer to the next RxD */
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#ifdef ENA_64BIT_SUP
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__le32 rxd_rbadr_hi ; /* physical tx buffer addr (high dword)*/
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#endif
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char far *rxd_virt ; /* virtual pointer to the data frag */
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/* virt pointer to the next RxD */
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struct s_smt_fp_rxd volatile far *rxd_next ;
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struct s_rxd_os rxd_os ; /* OS - specific struct */
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} ;
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/*
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* Descriptor Union Definition
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*/
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union s_fp_descr {
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struct s_smt_fp_txd t ; /* pointer to the TxD */
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struct s_smt_fp_rxd r ; /* pointer to the RxD */
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} ;
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/*
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* TxD Ring Control struct
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*/
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struct s_smt_tx_queue {
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struct s_smt_fp_txd volatile *tx_curr_put ; /* next free TxD */
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struct s_smt_fp_txd volatile *tx_prev_put ; /* shadow put pointer */
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struct s_smt_fp_txd volatile *tx_curr_get ; /* next TxD to release*/
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u_short tx_free ; /* count of free TxD's */
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u_short tx_used ; /* count of used TxD's */
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HW_PTR tx_bmu_ctl ; /* BMU addr for tx start */
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HW_PTR tx_bmu_dsc ; /* BMU addr for curr dsc. */
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} ;
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/*
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* RxD Ring Control struct
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*/
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struct s_smt_rx_queue {
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struct s_smt_fp_rxd volatile *rx_curr_put ; /* next RxD to queue into */
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struct s_smt_fp_rxd volatile *rx_prev_put ; /* shadow put pointer */
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struct s_smt_fp_rxd volatile *rx_curr_get ; /* next RxD to fill */
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u_short rx_free ; /* count of free RxD's */
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u_short rx_used ; /* count of used RxD's */
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HW_PTR rx_bmu_ctl ; /* BMU addr for rx start */
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HW_PTR rx_bmu_dsc ; /* BMU addr for curr dsc. */
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} ;
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#define VOID_FRAME_OFF 0x00
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#define CLAIM_FRAME_OFF 0x08
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#define BEACON_FRAME_OFF 0x10
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#define DBEACON_FRAME_OFF 0x18
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#define RX_FIFO_OFF 0x21 /* to get a prime number for */
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/* the RX_FIFO_SPACE */
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#define RBC_MEM_SIZE 0x8000
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#define SEND_ASYNC_AS_SYNC 0x1
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#define SYNC_TRAFFIC_ON 0x2
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/* big FIFO memory */
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#define RX_FIFO_SPACE 0x4000 - RX_FIFO_OFF
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#define TX_FIFO_SPACE 0x4000
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#define TX_SMALL_FIFO 0x0900
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#define TX_MEDIUM_FIFO TX_FIFO_SPACE / 2
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#define TX_LARGE_FIFO TX_FIFO_SPACE - TX_SMALL_FIFO
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#define RX_SMALL_FIFO 0x0900
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#define RX_LARGE_FIFO RX_FIFO_SPACE - RX_SMALL_FIFO
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struct s_smt_fifo_conf {
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u_short rbc_ram_start ; /* FIFO start address */
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u_short rbc_ram_end ; /* FIFO size */
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u_short rx1_fifo_start ; /* rx queue start address */
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u_short rx1_fifo_size ; /* rx queue size */
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u_short rx2_fifo_start ; /* rx queue start address */
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u_short rx2_fifo_size ; /* rx queue size */
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u_short tx_s_start ; /* sync queue start address */
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u_short tx_s_size ; /* sync queue size */
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u_short tx_a0_start ; /* async queue A0 start address */
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u_short tx_a0_size ; /* async queue A0 size */
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u_short fifo_config_mode ; /* FIFO configuration mode */
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} ;
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#define FM_ADDRX (FM_ADDET|FM_EXGPA0|FM_EXGPA1)
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struct s_smt_fp {
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u_short mdr2init ; /* mode register 2 init value */
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u_short mdr3init ; /* mode register 3 init value */
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u_short frselreg_init ; /* frame selection register init val */
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u_short rx_mode ; /* address mode broad/multi/promisc */
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u_short nsa_mode ;
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u_short rx_prom ;
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u_short exgpa ;
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struct err_st err_stats ; /* error statistics */
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/*
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* MAC buffers
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*/
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struct fddi_mac_sf { /* special frame build buffer */
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u_char mac_fc ;
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struct fddi_addr mac_dest ;
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struct fddi_addr mac_source ;
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u_char mac_info[0x20] ;
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} mac_sfb ;
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/*
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* queues
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*/
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#define QUEUE_S 0
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#define QUEUE_A0 1
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#define QUEUE_R1 0
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#define QUEUE_R2 1
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#define USED_QUEUES 2
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/*
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* queue pointers; points to the queue dependent variables
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*/
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struct s_smt_tx_queue *tx[USED_QUEUES] ;
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struct s_smt_rx_queue *rx[USED_QUEUES] ;
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/*
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* queue dependent variables
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*/
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struct s_smt_tx_queue tx_q[USED_QUEUES] ;
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struct s_smt_rx_queue rx_q[USED_QUEUES] ;
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/*
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* FIFO configuration struct
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*/
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struct s_smt_fifo_conf fifo ;
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/* last formac status */
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u_short s2u ;
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u_short s2l ;
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/* calculated FORMAC+ reg.addr. */
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HW_PTR fm_st1u ;
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HW_PTR fm_st1l ;
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HW_PTR fm_st2u ;
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HW_PTR fm_st2l ;
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HW_PTR fm_st3u ;
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HW_PTR fm_st3l ;
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/*
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* multicast table
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*/
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#define FPMAX_MULTICAST 32
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#define SMT_MAX_MULTI 4
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struct {
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struct s_fpmc {
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struct fddi_addr a ; /* mc address */
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u_char n ; /* usage counter */
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u_char perm ; /* flag: permanent */
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} table[FPMAX_MULTICAST] ;
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} mc ;
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struct fddi_addr group_addr ;
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u_long func_addr ; /* functional address */
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int smt_slots_used ; /* count of table entries for the SMT */
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int os_slots_used ; /* count of table entries */
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/* used by the os-specific module */
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} ;
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/*
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* modes for mac_set_rx_mode()
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*/
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#define RX_ENABLE_ALLMULTI 1 /* enable all multicasts */
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#define RX_DISABLE_ALLMULTI 2 /* disable "enable all multicasts" */
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#define RX_ENABLE_PROMISC 3 /* enable promiscuous */
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#define RX_DISABLE_PROMISC 4 /* disable promiscuous */
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#define RX_ENABLE_NSA 5 /* enable reception of NSA frames */
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#define RX_DISABLE_NSA 6 /* disable reception of NSA frames */
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/*
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* support for byte reversal in AIX
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* (descriptors and pointers must be byte reversed in memory
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* CPU is big endian; M-Channel is little endian)
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*/
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#ifdef AIX
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#define MDR_REV
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#define AIX_REVERSE(x) ((((x)<<24L)&0xff000000L) + \
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(((x)<< 8L)&0x00ff0000L) + \
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(((x)>> 8L)&0x0000ff00L) + \
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(((x)>>24L)&0x000000ffL))
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#else
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#ifndef AIX_REVERSE
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#define AIX_REVERSE(x) (x)
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#endif
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#endif
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#ifdef MDR_REV
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#define MDR_REVERSE(x) ((((x)<<24L)&0xff000000L) + \
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(((x)<< 8L)&0x00ff0000L) + \
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(((x)>> 8L)&0x0000ff00L) + \
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(((x)>>24L)&0x000000ffL))
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#else
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#ifndef MDR_REVERSE
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#define MDR_REVERSE(x) (x)
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#endif
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#endif
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#endif
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