425 lines
12 KiB
C
425 lines
12 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* Copyright (C) 2005-2014, 2018-2022 Intel Corporation
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* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
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* Copyright (C) 2016-2017 Intel Deutschland GmbH
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*/
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#ifndef __iwl_fw_api_debug_h__
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#define __iwl_fw_api_debug_h__
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/**
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* enum iwl_debug_cmds - debug commands
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*/
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enum iwl_debug_cmds {
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/**
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* @LMAC_RD_WR:
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* LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
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* &struct iwl_dbg_mem_access_rsp
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*/
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LMAC_RD_WR = 0x0,
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/**
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* @UMAC_RD_WR:
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* UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
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* &struct iwl_dbg_mem_access_rsp
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*/
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UMAC_RD_WR = 0x1,
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/**
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* @HOST_EVENT_CFG:
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* updates the enabled event severities
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* &struct iwl_dbg_host_event_cfg_cmd
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*/
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HOST_EVENT_CFG = 0x3,
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/**
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* @DBGC_SUSPEND_RESUME:
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* DBGC suspend/resume commad. Uses a single dword as data:
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* 0 - resume DBGC recording
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* 1 - suspend DBGC recording
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*/
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DBGC_SUSPEND_RESUME = 0x7,
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/**
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* @BUFFER_ALLOCATION:
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* passes DRAM buffers to a DBGC
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* &struct iwl_buf_alloc_cmd
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*/
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BUFFER_ALLOCATION = 0x8,
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/**
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* @FW_DUMP_COMPLETE_CMD:
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* sends command to fw once dump collection completed
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* &struct iwl_dbg_dump_complete_cmd
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*/
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FW_DUMP_COMPLETE_CMD = 0xB,
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/**
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* @MFU_ASSERT_DUMP_NTF:
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* &struct iwl_mfu_assert_dump_notif
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*/
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MFU_ASSERT_DUMP_NTF = 0xFE,
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};
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/* Error response/notification */
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enum {
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FW_ERR_UNKNOWN_CMD = 0x0,
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FW_ERR_INVALID_CMD_PARAM = 0x1,
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FW_ERR_SERVICE = 0x2,
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FW_ERR_ARC_MEMORY = 0x3,
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FW_ERR_ARC_CODE = 0x4,
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FW_ERR_WATCH_DOG = 0x5,
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FW_ERR_WEP_GRP_KEY_INDX = 0x10,
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FW_ERR_WEP_KEY_SIZE = 0x11,
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FW_ERR_OBSOLETE_FUNC = 0x12,
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FW_ERR_UNEXPECTED = 0xFE,
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FW_ERR_FATAL = 0xFF
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};
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/** enum iwl_dbg_suspend_resume_cmds - dbgc suspend resume operations
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* dbgc suspend resume command operations
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* @DBGC_RESUME_CMD: resume dbgc recording
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* @DBGC_SUSPEND_CMD: stop dbgc recording
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*/
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enum iwl_dbg_suspend_resume_cmds {
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DBGC_RESUME_CMD,
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DBGC_SUSPEND_CMD,
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};
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/**
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* struct iwl_error_resp - FW error indication
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* ( REPLY_ERROR = 0x2 )
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* @error_type: one of FW_ERR_*
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* @cmd_id: the command ID for which the error occurred
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* @reserved1: reserved
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* @bad_cmd_seq_num: sequence number of the erroneous command
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* @error_service: which service created the error, applicable only if
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* error_type = 2, otherwise 0
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* @timestamp: TSF in usecs.
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*/
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struct iwl_error_resp {
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__le32 error_type;
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u8 cmd_id;
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u8 reserved1;
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__le16 bad_cmd_seq_num;
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__le32 error_service;
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__le64 timestamp;
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} __packed;
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#define TX_FIFO_MAX_NUM_9000 8
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#define TX_FIFO_MAX_NUM 15
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#define RX_FIFO_MAX_NUM 2
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#define TX_FIFO_INTERNAL_MAX_NUM 6
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/**
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* struct iwl_shared_mem_cfg_v2 - Shared memory configuration information
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*
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* @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not
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* accessible)
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* @shared_mem_size: shared memory size
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* @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to
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* 0x0 as accessible only via DBGM RDAT)
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* @sample_buff_size: internal sample buff size
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* @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre
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* 8000 HW set to 0x0 as not accessible)
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* @txfifo_size: size of TXF0 ... TXF7
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* @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0
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* @page_buff_addr: used by UMAC and performance debug (page miss analysis),
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* when paging is not supported this should be 0
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* @page_buff_size: size of %page_buff_addr
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* @rxfifo_addr: Start address of rxFifo
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* @internal_txfifo_addr: start address of internalFifo
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* @internal_txfifo_size: internal fifos' size
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*
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* NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG
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* set, the last 3 members don't exist.
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*/
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struct iwl_shared_mem_cfg_v2 {
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__le32 shared_mem_addr;
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__le32 shared_mem_size;
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__le32 sample_buff_addr;
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__le32 sample_buff_size;
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__le32 txfifo_addr;
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__le32 txfifo_size[TX_FIFO_MAX_NUM_9000];
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__le32 rxfifo_size[RX_FIFO_MAX_NUM];
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__le32 page_buff_addr;
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__le32 page_buff_size;
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__le32 rxfifo_addr;
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__le32 internal_txfifo_addr;
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__le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM];
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} __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */
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/**
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* struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration
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*
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* @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB)
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* @txfifo_size: size of TX FIFOs
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* @rxfifo1_addr: RXF1 addr
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* @rxfifo1_size: RXF1 size
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*/
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struct iwl_shared_mem_lmac_cfg {
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__le32 txfifo_addr;
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__le32 txfifo_size[TX_FIFO_MAX_NUM];
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__le32 rxfifo1_addr;
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__le32 rxfifo1_size;
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} __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */
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/**
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* struct iwl_shared_mem_cfg - Shared memory configuration information
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*
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* @shared_mem_addr: shared memory address
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* @shared_mem_size: shared memory size
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* @sample_buff_addr: internal sample (mon/adc) buff addr
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* @sample_buff_size: internal sample buff size
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* @rxfifo2_addr: start addr of RXF2
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* @rxfifo2_size: size of RXF2
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* @page_buff_addr: used by UMAC and performance debug (page miss analysis),
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* when paging is not supported this should be 0
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* @page_buff_size: size of %page_buff_addr
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* @lmac_num: number of LMACs (1 or 2)
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* @lmac_smem: per - LMAC smem data
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* @rxfifo2_control_addr: start addr of RXF2C
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* @rxfifo2_control_size: size of RXF2C
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*/
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struct iwl_shared_mem_cfg {
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__le32 shared_mem_addr;
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__le32 shared_mem_size;
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__le32 sample_buff_addr;
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__le32 sample_buff_size;
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__le32 rxfifo2_addr;
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__le32 rxfifo2_size;
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__le32 page_buff_addr;
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__le32 page_buff_size;
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__le32 lmac_num;
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struct iwl_shared_mem_lmac_cfg lmac_smem[3];
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__le32 rxfifo2_control_addr;
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__le32 rxfifo2_control_size;
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} __packed; /* SHARED_MEM_ALLOC_API_S_VER_4 */
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/**
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* struct iwl_mfuart_load_notif_v1 - mfuart image version & status
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* ( MFUART_LOAD_NOTIFICATION = 0xb1 )
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* @installed_ver: installed image version
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* @external_ver: external image version
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* @status: MFUART loading status
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* @duration: MFUART loading time
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*/
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struct iwl_mfuart_load_notif_v1 {
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__le32 installed_ver;
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__le32 external_ver;
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__le32 status;
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__le32 duration;
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} __packed; /* MFU_LOADER_NTFY_API_S_VER_1 */
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/**
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* struct iwl_mfuart_load_notif - mfuart image version & status
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* ( MFUART_LOAD_NOTIFICATION = 0xb1 )
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* @installed_ver: installed image version
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* @external_ver: external image version
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* @status: MFUART loading status
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* @duration: MFUART loading time
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* @image_size: MFUART image size in bytes
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*/
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struct iwl_mfuart_load_notif {
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__le32 installed_ver;
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__le32 external_ver;
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__le32 status;
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__le32 duration;
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/* image size valid only in v2 of the command */
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__le32 image_size;
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} __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */
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/**
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* struct iwl_mfu_assert_dump_notif - mfuart dump logs
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* ( MFU_ASSERT_DUMP_NTF = 0xfe )
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* @assert_id: mfuart assert id that cause the notif
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* @curr_reset_num: number of asserts since uptime
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* @index_num: current chunk id
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* @parts_num: total number of chunks
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* @data_size: number of data bytes sent
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* @data: data buffer
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*/
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struct iwl_mfu_assert_dump_notif {
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__le32 assert_id;
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__le32 curr_reset_num;
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__le16 index_num;
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__le16 parts_num;
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__le32 data_size;
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__le32 data[];
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} __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */
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/**
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* enum iwl_mvm_marker_id - marker ids
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*
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* The ids for different type of markers to insert into the usniffer logs
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*
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* @MARKER_ID_TX_FRAME_LATENCY: TX latency marker
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* @MARKER_ID_SYNC_CLOCK: sync FW time and systime
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*/
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enum iwl_mvm_marker_id {
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MARKER_ID_TX_FRAME_LATENCY = 1,
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MARKER_ID_SYNC_CLOCK = 2,
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}; /* MARKER_ID_API_E_VER_2 */
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/**
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* struct iwl_mvm_marker - mark info into the usniffer logs
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*
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* (MARKER_CMD = 0xcb)
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*
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* Mark the UTC time stamp into the usniffer logs together with additional
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* metadata, so the usniffer output can be parsed.
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* In the command response the ucode will return the GP2 time.
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*
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* @dw_len: The amount of dwords following this byte including this byte.
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* @marker_id: A unique marker id (iwl_mvm_marker_id).
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* @reserved: reserved.
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* @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC
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* @metadata: additional meta data that will be written to the unsiffer log
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*/
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struct iwl_mvm_marker {
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u8 dw_len;
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u8 marker_id;
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__le16 reserved;
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__le64 timestamp;
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__le32 metadata[];
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} __packed; /* MARKER_API_S_VER_1 */
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/**
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* struct iwl_mvm_marker_rsp - Response to marker cmd
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*
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* @gp2: The gp2 clock value in the FW
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*/
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struct iwl_mvm_marker_rsp {
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__le32 gp2;
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} __packed;
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/* Operation types for the debug mem access */
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enum {
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DEBUG_MEM_OP_READ = 0,
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DEBUG_MEM_OP_WRITE = 1,
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DEBUG_MEM_OP_WRITE_BYTES = 2,
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};
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#define DEBUG_MEM_MAX_SIZE_DWORDS 32
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/**
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* struct iwl_dbg_mem_access_cmd - Request the device to read/write memory
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* @op: DEBUG_MEM_OP_*
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* @addr: address to read/write from/to
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* @len: in dwords, to read/write
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* @data: for write opeations, contains the source buffer
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*/
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struct iwl_dbg_mem_access_cmd {
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__le32 op;
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__le32 addr;
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__le32 len;
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__le32 data[];
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} __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */
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/* Status responses for the debug mem access */
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enum {
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DEBUG_MEM_STATUS_SUCCESS = 0x0,
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DEBUG_MEM_STATUS_FAILED = 0x1,
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DEBUG_MEM_STATUS_LOCKED = 0x2,
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DEBUG_MEM_STATUS_HIDDEN = 0x3,
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DEBUG_MEM_STATUS_LENGTH = 0x4,
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};
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/**
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* struct iwl_dbg_mem_access_rsp - Response to debug mem commands
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* @status: DEBUG_MEM_STATUS_*
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* @len: read dwords (0 for write operations)
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* @data: contains the read DWs
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*/
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struct iwl_dbg_mem_access_rsp {
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__le32 status;
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__le32 len;
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__le32 data[];
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} __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */
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/**
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* struct iwl_dbg_suspend_resume_cmd - dbgc suspend resume command
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* @operation: suspend or resume operation, uses
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* &enum iwl_dbg_suspend_resume_cmds
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*/
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struct iwl_dbg_suspend_resume_cmd {
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__le32 operation;
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} __packed;
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#define BUF_ALLOC_MAX_NUM_FRAGS 16
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/**
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* struct iwl_buf_alloc_frag - a DBGC fragment
|
||
|
|
* @addr: base address of the fragment
|
||
|
|
* @size: size of the fragment
|
||
|
|
*/
|
||
|
|
struct iwl_buf_alloc_frag {
|
||
|
|
__le64 addr;
|
||
|
|
__le32 size;
|
||
|
|
} __packed; /* FRAGMENT_STRUCTURE_API_S_VER_1 */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* struct iwl_buf_alloc_cmd - buffer allocation command
|
||
|
|
* @alloc_id: &enum iwl_fw_ini_allocation_id
|
||
|
|
* @buf_location: &enum iwl_fw_ini_buffer_location
|
||
|
|
* @num_frags: number of fragments
|
||
|
|
* @frags: fragments array
|
||
|
|
*/
|
||
|
|
struct iwl_buf_alloc_cmd {
|
||
|
|
__le32 alloc_id;
|
||
|
|
__le32 buf_location;
|
||
|
|
__le32 num_frags;
|
||
|
|
struct iwl_buf_alloc_frag frags[BUF_ALLOC_MAX_NUM_FRAGS];
|
||
|
|
} __packed; /* BUFFER_ALLOCATION_CMD_API_S_VER_2 */
|
||
|
|
|
||
|
|
#define DRAM_INFO_FIRST_MAGIC_WORD 0x76543210
|
||
|
|
#define DRAM_INFO_SECOND_MAGIC_WORD 0x89ABCDEF
|
||
|
|
|
||
|
|
/**
|
||
|
|
* struct iwL_dram_info - DRAM fragments allocation struct
|
||
|
|
*
|
||
|
|
* Driver will fill in the first 1K(+) of the pointed DRAM fragment
|
||
|
|
*
|
||
|
|
* @first_word: magic word value
|
||
|
|
* @second_word: magic word value
|
||
|
|
* @framfrags: DRAM fragmentaion detail
|
||
|
|
*/
|
||
|
|
struct iwl_dram_info {
|
||
|
|
__le32 first_word;
|
||
|
|
__le32 second_word;
|
||
|
|
struct iwl_buf_alloc_cmd dram_frags[IWL_FW_INI_ALLOCATION_NUM - 1];
|
||
|
|
} __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* struct iwl_dbgc1_info - DBGC1 address and size
|
||
|
|
*
|
||
|
|
* Driver will fill the dbcg1 address and size at address based on config TLV.
|
||
|
|
*
|
||
|
|
* @first_word: all 0 set as identifier
|
||
|
|
* @dbgc1_add_lsb: LSB bits of DBGC1 physical address
|
||
|
|
* @dbgc1_add_msb: MSB bits of DBGC1 physical address
|
||
|
|
* @dbgc1_size: DBGC1 size
|
||
|
|
*/
|
||
|
|
struct iwl_dbgc1_info {
|
||
|
|
__le32 first_word;
|
||
|
|
__le32 dbgc1_add_lsb;
|
||
|
|
__le32 dbgc1_add_msb;
|
||
|
|
__le32 dbgc1_size;
|
||
|
|
} __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* struct iwl_dbg_host_event_cfg_cmd
|
||
|
|
* @enabled_severities: enabled severities
|
||
|
|
*/
|
||
|
|
struct iwl_dbg_host_event_cfg_cmd {
|
||
|
|
__le32 enabled_severities;
|
||
|
|
} __packed; /* DEBUG_HOST_EVENT_CFG_CMD_API_S_VER_1 */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* struct iwl_dbg_dump_complete_cmd - dump complete cmd
|
||
|
|
*
|
||
|
|
* @tp: timepoint whose dump has completed
|
||
|
|
* @tp_data: timepoint data
|
||
|
|
*/
|
||
|
|
struct iwl_dbg_dump_complete_cmd {
|
||
|
|
__le32 tp;
|
||
|
|
__le32 tp_data;
|
||
|
|
} __packed; /* FW_DUMP_COMPLETE_CMD_API_S_VER_1 */
|
||
|
|
|
||
|
|
#endif /* __iwl_fw_api_debug_h__ */
|