264 lines
7.0 KiB
C
264 lines
7.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (C) 2017 Intel Deutschland GmbH
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* Copyright (C) 2018-2021 Intel Corporation
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*/
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#include "iwl-trans.h"
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#include "iwl-fh.h"
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#include "iwl-context-info.h"
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#include "internal.h"
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#include "iwl-prph.h"
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static void *_iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
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size_t size,
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dma_addr_t *phys,
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int depth)
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{
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void *result;
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if (WARN(depth > 2,
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"failed to allocate DMA memory not crossing 2^32 boundary"))
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return NULL;
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result = dma_alloc_coherent(trans->dev, size, phys, GFP_KERNEL);
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if (!result)
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return NULL;
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if (unlikely(iwl_txq_crosses_4g_boundary(*phys, size))) {
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void *old = result;
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dma_addr_t oldphys = *phys;
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result = _iwl_pcie_ctxt_info_dma_alloc_coherent(trans, size,
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phys,
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depth + 1);
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dma_free_coherent(trans->dev, size, old, oldphys);
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}
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return result;
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}
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static void *iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
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size_t size,
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dma_addr_t *phys)
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{
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return _iwl_pcie_ctxt_info_dma_alloc_coherent(trans, size, phys, 0);
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}
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int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
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const void *data, u32 len,
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struct iwl_dram_data *dram)
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{
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dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len,
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&dram->physical);
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if (!dram->block)
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return -ENOMEM;
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dram->size = len;
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memcpy(dram->block, data, len);
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return 0;
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}
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void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans)
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{
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struct iwl_self_init_dram *dram = &trans->init_dram;
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int i;
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if (!dram->paging) {
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WARN_ON(dram->paging_cnt);
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return;
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}
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/* free paging*/
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for (i = 0; i < dram->paging_cnt; i++)
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dma_free_coherent(trans->dev, dram->paging[i].size,
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dram->paging[i].block,
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dram->paging[i].physical);
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kfree(dram->paging);
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dram->paging_cnt = 0;
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dram->paging = NULL;
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}
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int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
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const struct fw_img *fw,
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struct iwl_context_info_dram *ctxt_dram)
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{
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struct iwl_self_init_dram *dram = &trans->init_dram;
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int i, ret, lmac_cnt, umac_cnt, paging_cnt;
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if (WARN(dram->paging,
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"paging shouldn't already be initialized (%d pages)\n",
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dram->paging_cnt))
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iwl_pcie_ctxt_info_free_paging(trans);
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lmac_cnt = iwl_pcie_get_num_sections(fw, 0);
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/* add 1 due to separator */
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umac_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + 1);
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/* add 2 due to separators */
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paging_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + umac_cnt + 2);
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dram->fw = kcalloc(umac_cnt + lmac_cnt, sizeof(*dram->fw), GFP_KERNEL);
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if (!dram->fw)
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return -ENOMEM;
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dram->paging = kcalloc(paging_cnt, sizeof(*dram->paging), GFP_KERNEL);
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if (!dram->paging)
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return -ENOMEM;
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/* initialize lmac sections */
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for (i = 0; i < lmac_cnt; i++) {
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ret = iwl_pcie_ctxt_info_alloc_dma(trans, fw->sec[i].data,
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fw->sec[i].len,
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&dram->fw[dram->fw_cnt]);
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if (ret)
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return ret;
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ctxt_dram->lmac_img[i] =
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cpu_to_le64(dram->fw[dram->fw_cnt].physical);
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dram->fw_cnt++;
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}
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/* initialize umac sections */
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for (i = 0; i < umac_cnt; i++) {
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/* access FW with +1 to make up for lmac separator */
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ret = iwl_pcie_ctxt_info_alloc_dma(trans,
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fw->sec[dram->fw_cnt + 1].data,
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fw->sec[dram->fw_cnt + 1].len,
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&dram->fw[dram->fw_cnt]);
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if (ret)
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return ret;
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ctxt_dram->umac_img[i] =
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cpu_to_le64(dram->fw[dram->fw_cnt].physical);
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dram->fw_cnt++;
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}
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/*
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* Initialize paging.
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* Paging memory isn't stored in dram->fw as the umac and lmac - it is
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* stored separately.
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* This is since the timing of its release is different -
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* while fw memory can be released on alive, the paging memory can be
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* freed only when the device goes down.
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* Given that, the logic here in accessing the fw image is a bit
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* different - fw_cnt isn't changing so loop counter is added to it.
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*/
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for (i = 0; i < paging_cnt; i++) {
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/* access FW with +2 to make up for lmac & umac separators */
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int fw_idx = dram->fw_cnt + i + 2;
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ret = iwl_pcie_ctxt_info_alloc_dma(trans, fw->sec[fw_idx].data,
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fw->sec[fw_idx].len,
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&dram->paging[i]);
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if (ret)
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return ret;
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ctxt_dram->virtual_img[i] =
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cpu_to_le64(dram->paging[i].physical);
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dram->paging_cnt++;
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}
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return 0;
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}
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int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
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const struct fw_img *fw)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_context_info *ctxt_info;
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struct iwl_context_info_rbd_cfg *rx_cfg;
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u32 control_flags = 0, rb_size;
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dma_addr_t phys;
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int ret;
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ctxt_info = iwl_pcie_ctxt_info_dma_alloc_coherent(trans,
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sizeof(*ctxt_info),
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&phys);
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if (!ctxt_info)
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return -ENOMEM;
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trans_pcie->ctxt_info_dma_addr = phys;
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ctxt_info->version.version = 0;
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ctxt_info->version.mac_id =
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cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
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/* size is in DWs */
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ctxt_info->version.size = cpu_to_le16(sizeof(*ctxt_info) / 4);
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switch (trans_pcie->rx_buf_size) {
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case IWL_AMSDU_2K:
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rb_size = IWL_CTXT_INFO_RB_SIZE_2K;
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break;
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case IWL_AMSDU_4K:
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rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
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break;
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case IWL_AMSDU_8K:
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rb_size = IWL_CTXT_INFO_RB_SIZE_8K;
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break;
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case IWL_AMSDU_12K:
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rb_size = IWL_CTXT_INFO_RB_SIZE_16K;
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break;
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default:
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WARN_ON(1);
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rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
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}
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WARN_ON(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds) > 12);
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control_flags = IWL_CTXT_INFO_TFD_FORMAT_LONG;
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control_flags |=
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u32_encode_bits(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds),
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IWL_CTXT_INFO_RB_CB_SIZE);
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control_flags |= u32_encode_bits(rb_size, IWL_CTXT_INFO_RB_SIZE);
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ctxt_info->control.control_flags = cpu_to_le32(control_flags);
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/* initialize RX default queue */
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rx_cfg = &ctxt_info->rbd_cfg;
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rx_cfg->free_rbd_addr = cpu_to_le64(trans_pcie->rxq->bd_dma);
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rx_cfg->used_rbd_addr = cpu_to_le64(trans_pcie->rxq->used_bd_dma);
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rx_cfg->status_wr_ptr = cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
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/* initialize TX command queue */
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ctxt_info->hcmd_cfg.cmd_queue_addr =
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cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr);
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ctxt_info->hcmd_cfg.cmd_queue_size =
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TFD_QUEUE_CB_SIZE(IWL_CMD_QUEUE_SIZE);
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/* allocate ucode sections in dram and set addresses */
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ret = iwl_pcie_init_fw_sec(trans, fw, &ctxt_info->dram);
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if (ret) {
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dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
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ctxt_info, trans_pcie->ctxt_info_dma_addr);
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return ret;
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}
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trans_pcie->ctxt_info = ctxt_info;
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iwl_enable_fw_load_int_ctx_info(trans);
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/* Configure debug, if exists */
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if (iwl_pcie_dbg_on(trans))
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iwl_pcie_apply_destination(trans);
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/* kick FW self load */
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iwl_write64(trans, CSR_CTXT_INFO_BA, trans_pcie->ctxt_info_dma_addr);
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/* Context info will be released upon alive or failure to get one */
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return 0;
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}
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void iwl_pcie_ctxt_info_free(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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if (!trans_pcie->ctxt_info)
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return;
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dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
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trans_pcie->ctxt_info,
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trans_pcie->ctxt_info_dma_addr);
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trans_pcie->ctxt_info_dma_addr = 0;
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trans_pcie->ctxt_info = NULL;
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iwl_pcie_ctxt_info_free_fw_img(trans);
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}
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