230 lines
7.1 KiB
C
230 lines
7.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2009-2014 Realtek Corporation.*/
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#ifndef __RTL92E_DM_H__
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#define __RTL92E_DM_H__
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#define OFDMCCA_TH 500
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#define BW_IND_BIAS 500
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#define MF_USC 2
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#define MF_LSC 1
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#define MF_USC_LSC 0
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#define MONITOR_TIME 30
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#define MAIN_ANT 0
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#define AUX_ANT 1
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#define MAIN_ANT_CG_TRX 1
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#define AUX_ANT_CG_TRX 0
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#define MAIN_ANT_CGCS_RX 0
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#define AUX_ANT_CGCS_RX 1
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/*RF REG LIST*/
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#define DM_REG_RF_MODE_11N 0x00
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#define DM_REG_RF_0B_11N 0x0B
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#define DM_REG_CHNBW_11N 0x18
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#define DM_REG_T_METER_11N 0x24
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#define DM_REG_RF_25_11N 0x25
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#define DM_REG_RF_26_11N 0x26
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#define DM_REG_RF_27_11N 0x27
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#define DM_REG_RF_2B_11N 0x2B
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#define DM_REG_RF_2C_11N 0x2C
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#define DM_REG_RXRF_A3_11N 0x3C
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#define DM_REG_T_METER_92D_11N 0x42
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#define DM_REG_T_METER_92E_11N 0x42
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/*BB REG LIST*/
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/*PAGE 8 */
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#define DM_REG_BB_CTRL_11N 0x800
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#define DM_REG_RF_PIN_11N 0x804
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#define DM_REG_PSD_CTRL_11N 0x808
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#define DM_REG_TX_ANT_CTRL_11N 0x80C
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#define DM_REG_BB_PWR_SAV5_11N 0x818
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#define DM_REG_CCK_RPT_FORMAT_11N 0x824
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#define DM_REG_RX_DEFUALT_A_11N 0x858
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#define DM_REG_RX_DEFUALT_B_11N 0x85A
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#define DM_REG_BB_PWR_SAV3_11N 0x85C
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#define DM_REG_ANTSEL_CTRL_11N 0x860
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#define DM_REG_RX_ANT_CTRL_11N 0x864
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#define DM_REG_PIN_CTRL_11N 0x870
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#define DM_REG_BB_PWR_SAV1_11N 0x874
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#define DM_REG_ANTSEL_PATH_11N 0x878
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#define DM_REG_BB_3WIRE_11N 0x88C
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#define DM_REG_SC_CNT_11N 0x8C4
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#define DM_REG_PSD_DATA_11N 0x8B4
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/*PAGE 9*/
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#define DM_REG_ANT_MAPPING1_11N 0x914
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#define DM_REG_ANT_MAPPING2_11N 0x918
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/*PAGE A*/
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#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00
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#define DM_REG_CCK_CCA_11N 0xA0A
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#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
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#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10
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#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14
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#define DM_REG_CCK_FILTER_PARA1_11N 0xA22
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#define DM_REG_CCK_FILTER_PARA2_11N 0xA23
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#define DM_REG_CCK_FILTER_PARA3_11N 0xA24
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#define DM_REG_CCK_FILTER_PARA4_11N 0xA25
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#define DM_REG_CCK_FILTER_PARA5_11N 0xA26
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#define DM_REG_CCK_FILTER_PARA6_11N 0xA27
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#define DM_REG_CCK_FILTER_PARA7_11N 0xA28
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#define DM_REG_CCK_FILTER_PARA8_11N 0xA29
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#define DM_REG_CCK_FA_RST_11N 0xA2C
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#define DM_REG_CCK_FA_MSB_11N 0xA58
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#define DM_REG_CCK_FA_LSB_11N 0xA5C
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#define DM_REG_CCK_CCA_CNT_11N 0xA60
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#define DM_REG_BB_PWR_SAV4_11N 0xA74
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/*PAGE B */
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#define DM_REG_LNA_SWITCH_11N 0xB2C
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#define DM_REG_PATH_SWITCH_11N 0xB30
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#define DM_REG_RSSI_CTRL_11N 0xB38
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#define DM_REG_CONFIG_ANTA_11N 0xB68
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#define DM_REG_RSSI_BT_11N 0xB9C
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/*PAGE C */
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#define DM_REG_OFDM_FA_HOLDC_11N 0xC00
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#define DM_REG_RX_PATH_11N 0xC04
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#define DM_REG_TRMUX_11N 0xC08
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#define DM_REG_OFDM_FA_RSTC_11N 0xC0C
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#define DM_REG_RXIQI_MATRIX_11N 0xC14
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#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
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#define DM_REG_IGI_A_11N 0xC50
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#define DM_REG_ANTDIV_PARA2_11N 0xC54
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#define DM_REG_IGI_B_11N 0xC58
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#define DM_REG_ANTDIV_PARA3_11N 0xC5C
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#define DM_REG_L1SBD_PD_CH_11N 0XC6C
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#define DM_REG_BB_PWR_SAV2_11N 0xC70
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#define DM_REG_RX_OFF_11N 0xC7C
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#define DM_REG_TXIQK_MATRIXA_11N 0xC80
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#define DM_REG_TXIQK_MATRIXB_11N 0xC88
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#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
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#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
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#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
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#define DM_REG_ANTDIV_PARA1_11N 0xCA4
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#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0
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/*PAGE D */
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#define DM_REG_OFDM_FA_RSTD_11N 0xD00
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#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0
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#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4
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#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8
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/*PAGE E */
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#define DM_REG_TXAGC_A_6_18_11N 0xE00
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#define DM_REG_TXAGC_A_24_54_11N 0xE04
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#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08
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#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10
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#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14
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#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18
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#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C
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#define DM_REG_FPGA0_IQK_11N 0xE28
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#define DM_REG_TXIQK_TONE_A_11N 0xE30
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#define DM_REG_RXIQK_TONE_A_11N 0xE34
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#define DM_REG_TXIQK_PI_A_11N 0xE38
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#define DM_REG_RXIQK_PI_A_11N 0xE3C
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#define DM_REG_TXIQK_11N 0xE40
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#define DM_REG_RXIQK_11N 0xE44
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#define DM_REG_IQK_AGC_PTS_11N 0xE48
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#define DM_REG_IQK_AGC_RSP_11N 0xE4C
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#define DM_REG_BLUETOOTH_11N 0xE6C
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#define DM_REG_RX_WAIT_CCA_11N 0xE70
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#define DM_REG_TX_CCK_RFON_11N 0xE74
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#define DM_REG_TX_CCK_BBON_11N 0xE78
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#define DM_REG_OFDM_RFON_11N 0xE7C
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#define DM_REG_OFDM_BBON_11N 0xE80
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#define DM_REG_TX2RX_11N 0xE84
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#define DM_REG_TX2TX_11N 0xE88
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#define DM_REG_RX_CCK_11N 0xE8C
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#define DM_REG_RX_OFDM_11N 0xED0
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#define DM_REG_RX_WAIT_RIFS_11N 0xED4
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#define DM_REG_RX2RX_11N 0xED8
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#define DM_REG_STANDBY_11N 0xEDC
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#define DM_REG_SLEEP_11N 0xEE0
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#define DM_REG_PMPD_ANAEN_11N 0xEEC
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/*MAC REG LIST*/
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#define DM_REG_BB_RST_11N 0x02
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#define DM_REG_ANTSEL_PIN_11N 0x4C
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#define DM_REG_EARLY_MODE_11N 0x4D0
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#define DM_REG_RSSI_MONITOR_11N 0x4FE
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#define DM_REG_EDCA_VO_11N 0x500
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#define DM_REG_EDCA_VI_11N 0x504
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#define DM_REG_EDCA_BE_11N 0x508
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#define DM_REG_EDCA_BK_11N 0x50C
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#define DM_REG_TXPAUSE_11N 0x522
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#define DM_REG_RESP_TX_11N 0x6D8
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#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0
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#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4
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/*DIG Related*/
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#define DM_BIT_IGI_11N 0x0000007F
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#define HAL_DM_DIG_DISABLE BIT(0)
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#define HAL_DM_HIPWR_DISABLE BIT(1)
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#define OFDM_TABLE_LENGTH 43
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#define CCK_TABLE_LENGTH 33
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#define OFDM_TABLE_SIZE 43
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#define CCK_TABLE_SIZE 33
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#define BW_AUTO_SWITCH_HIGH_LOW 25
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#define BW_AUTO_SWITCH_LOW_HIGH 30
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#define DM_DIG_FA_UPPER 0x3e
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#define DM_DIG_FA_LOWER 0x1e
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#define DM_DIG_FA_TH0 0x200
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#define DM_DIG_FA_TH1 0x300
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#define DM_DIG_FA_TH2 0x400
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#define RXPATHSELECTION_SS_TH_LOW 30
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#define RXPATHSELECTION_DIFF_TH 18
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#define DM_RATR_STA_INIT 0
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#define DM_RATR_STA_HIGH 1
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#define DM_RATR_STA_MIDDLE 2
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#define DM_RATR_STA_LOW 3
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#define CTS2SELF_THVAL 30
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#define REGC38_TH 20
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#define WAIOTTHVAL 25
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#define TXHIGHPWRLEVEL_NORMAL 0
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#define TXHIGHPWRLEVEL_LEVEL1 1
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#define TXHIGHPWRLEVEL_LEVEL2 2
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#define TXHIGHPWRLEVEL_BT1 3
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#define TXHIGHPWRLEVEL_BT2 4
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#define DM_TYPE_BYFW 0
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#define DM_TYPE_BYDRIVER 1
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#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
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#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
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#define TXPWRTRACK_MAX_IDX 6
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/* Dynamic ATC switch */
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#define ATC_STATUS_OFF 0x0 /* enable */
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#define ATC_STATUS_ON 0x1 /* disable */
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#define CFO_THRESHOLD_XTAL 10 /* kHz */
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#define CFO_THRESHOLD_ATC 80 /* kHz */
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/* RSSI Dump Message */
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#define RA_RSSIDUMP 0xcb0
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#define RB_RSSIDUMP 0xcb1
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#define RS1_RXEVMDUMP 0xcb2
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#define RS2_RXEVMDUMP 0xcb3
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#define RA_RXSNRDUMP 0xcb4
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#define RB_RXSNRDUMP 0xcb5
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#define RA_CFOSHORTDUMP 0xcb6
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#define RB_CFOSHORTDUMP 0xcb8
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#define RA_CFOLONGDUMP 0xcba
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#define RB_CFOLONGDUMP 0xcbc
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void rtl92ee_dm_init(struct ieee80211_hw *hw);
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void rtl92ee_dm_watchdog(struct ieee80211_hw *hw);
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void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw,
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u8 cur_thres);
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void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
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void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw);
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void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
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void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw,
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u8 rate, bool collision_state);
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#endif
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