432 lines
10 KiB
C
432 lines
10 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2009-2012 Realtek Corporation.*/
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#ifndef __REALTEK_92S_DEF_H__
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#define __REALTEK_92S_DEF_H__
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#define RX_MPDU_QUEUE 0
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#define RX_CMD_QUEUE 1
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#define SHORT_SLOT_TIME 9
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#define NON_SHORT_SLOT_TIME 20
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/* Queue Select Value in TxDesc */
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#define QSLT_BK 0x2
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#define QSLT_BE 0x0
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#define QSLT_VI 0x5
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#define QSLT_VO 0x6
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#define QSLT_BEACON 0x10
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#define QSLT_HIGH 0x11
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#define QSLT_MGNT 0x12
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#define QSLT_CMD 0x13
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/* Tx Desc */
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#define TX_DESC_SIZE_RTL8192S (16 * 4)
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#define TX_CMDDESC_SIZE_RTL8192S (16 * 4)
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/* macros to read/write various fields in RX or TX descriptors */
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/* Dword 0 */
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static inline void set_tx_desc_pkt_size(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));
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}
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static inline void set_tx_desc_offset(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));
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}
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static inline void set_tx_desc_last_seg(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits(__pdesc, __val, BIT(26));
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}
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static inline void set_tx_desc_first_seg(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits(__pdesc, __val, BIT(27));
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}
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static inline void set_tx_desc_linip(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits(__pdesc, __val, BIT(28));
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}
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static inline void set_tx_desc_own(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits(__pdesc, __val, BIT(31));
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}
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static inline u32 get_tx_desc_own(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc), BIT(31));
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}
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/* Dword 1 */
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static inline void set_tx_desc_macid(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0));
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}
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static inline void set_tx_desc_queue_sel(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));
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}
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static inline void set_tx_desc_non_qos(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 1), __val, BIT(16));
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}
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static inline void set_tx_desc_sec_type(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));
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}
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/* Dword 2 */
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static inline void set_tx_desc_rsvd_macid(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 2), __val, GENMASK(28, 24));
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}
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static inline void set_tx_desc_agg_enable(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 2), __val, BIT(29));
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}
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/* Dword 3 */
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static inline void set_tx_desc_seq(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16));
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}
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/* Dword 4 */
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static inline void set_tx_desc_rts_rate(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 4), __val, GENMASK(5, 0));
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}
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static inline void set_tx_desc_cts_enable(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 4), __val, BIT(11));
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}
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static inline void set_tx_desc_rts_enable(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 4), __val, BIT(12));
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}
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static inline void set_tx_desc_ra_brsr_id(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 4), __val, GENMASK(15, 13));
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}
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static inline void set_tx_desc_txht(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 4), __val, BIT(16));
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}
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static inline void set_tx_desc_tx_short(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 4), __val, BIT(17));
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}
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static inline void set_tx_desc_tx_bandwidth(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 4), __val, BIT(18));
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}
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static inline void set_tx_desc_tx_sub_carrier(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 4), __val, GENMASK(20, 19));
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}
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static inline void set_tx_desc_rts_short(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 4), __val, BIT(25));
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}
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static inline void set_tx_desc_rts_bandwidth(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 4), __val, BIT(26));
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}
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static inline void set_tx_desc_rts_sub_carrier(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 4), __val, GENMASK(28, 27));
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}
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static inline void set_tx_desc_rts_stbc(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 4), __val, GENMASK(30, 29));
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}
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static inline void set_tx_desc_user_rate(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 4), __val, BIT(31));
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}
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/* Dword 5 */
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static inline void set_tx_desc_packet_id(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 5), __val, GENMASK(8, 0));
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}
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static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 5), __val, GENMASK(14, 9));
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}
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static inline void set_tx_desc_data_rate_fb_limit(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 5), __val, GENMASK(20, 16));
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}
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/* Dword 7 */
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static inline void set_tx_desc_tx_buffer_size(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));
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}
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/* Dword 8 */
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static inline void set_tx_desc_tx_buffer_address(__le32 *__pdesc, u32 __val)
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{
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*(__pdesc + 8) = cpu_to_le32(__val);
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}
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static inline u32 get_tx_desc_tx_buffer_address(__le32 *__pdesc)
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{
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return le32_to_cpu(*((__pdesc + 8)));
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}
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/* Dword 9 */
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static inline void set_tx_desc_next_desc_address(__le32 *__pdesc, u32 __val)
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{
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*(__pdesc + 9) = cpu_to_le32(__val);
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}
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/* Because the PCI Tx descriptors are chaied at the
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* initialization and all the NextDescAddresses in
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* these descriptors cannot not be cleared (,or
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* driver/HW cannot find the next descriptor), the
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* offset 36 (NextDescAddresses) is reserved when
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* the desc is cleared. */
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#define TX_DESC_NEXT_DESC_OFFSET 36
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#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
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memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET))
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/* Rx Desc */
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#define RX_STATUS_DESC_SIZE 24
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#define RX_DRV_INFO_SIZE_UNIT 8
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/* DWORD 0 */
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static inline void set_rx_status_desc_pkt_len(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));
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}
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static inline void set_rx_status_desc_eor(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits(__pdesc, __val, BIT(30));
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}
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static inline void set_rx_status_desc_own(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits(__pdesc, __val, BIT(31));
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}
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static inline u32 get_rx_status_desc_pkt_len(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc), GENMASK(13, 0));
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}
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static inline u32 get_rx_status_desc_crc32(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc), BIT(14));
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}
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static inline u32 get_rx_status_desc_icv(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc), BIT(15));
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}
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static inline u32 get_rx_status_desc_drvinfo_size(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc), GENMASK(19, 16));
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}
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static inline u32 get_rx_status_desc_shift(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc), GENMASK(25, 24));
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}
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static inline u32 get_rx_status_desc_phy_status(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc), BIT(26));
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}
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static inline u32 get_rx_status_desc_swdec(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc), BIT(27));
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}
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static inline u32 get_rx_status_desc_own(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc), BIT(31));
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}
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/* DWORD 1 */
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static inline u32 get_rx_status_desc_paggr(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc + 1), BIT(14));
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}
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static inline u32 get_rx_status_desc_faggr(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc + 1), BIT(15));
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}
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/* DWORD 3 */
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static inline u32 get_rx_status_desc_rx_mcs(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0));
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}
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static inline u32 get_rx_status_desc_rx_ht(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc + 3), BIT(6));
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}
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static inline u32 get_rx_status_desc_splcp(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc + 3), BIT(8));
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}
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static inline u32 get_rx_status_desc_bw(__le32 *__pdesc)
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{
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return le32_get_bits(*(__pdesc + 3), BIT(9));
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}
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/* DWORD 5 */
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static inline u32 get_rx_status_desc_tsfl(__le32 *__pdesc)
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{
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return le32_to_cpu(*((__pdesc + 5)));
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}
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/* DWORD 6 */
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static inline void set_rx_status__desc_buff_addr(__le32 *__pdesc, u32 __val)
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{
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*(__pdesc + 6) = cpu_to_le32(__val);
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}
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static inline u32 get_rx_status_desc_buff_addr(__le32 *__pdesc)
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{
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return le32_to_cpu(*(__pdesc + 6));
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}
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#define SE_RX_HAL_IS_CCK_RATE(_pdesc)\
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(get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE1M || \
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get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE2M || \
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get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE5_5M ||\
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get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE11M)
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enum rf_optype {
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RF_OP_BY_SW_3WIRE = 0,
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RF_OP_BY_FW,
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RF_OP_MAX
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};
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enum ic_inferiority {
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IC_INFERIORITY_A = 0,
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IC_INFERIORITY_B = 1,
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};
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enum fwcmd_iotype {
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/* For DIG DM */
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FW_CMD_DIG_ENABLE = 0,
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FW_CMD_DIG_DISABLE = 1,
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FW_CMD_DIG_HALT = 2,
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FW_CMD_DIG_RESUME = 3,
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/* For High Power DM */
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FW_CMD_HIGH_PWR_ENABLE = 4,
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FW_CMD_HIGH_PWR_DISABLE = 5,
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/* For Rate adaptive DM */
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FW_CMD_RA_RESET = 6,
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FW_CMD_RA_ACTIVE = 7,
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FW_CMD_RA_REFRESH_N = 8,
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|
FW_CMD_RA_REFRESH_BG = 9,
|
||
|
|
FW_CMD_RA_INIT = 10,
|
||
|
|
/* For FW supported IQK */
|
||
|
|
FW_CMD_IQK_INIT = 11,
|
||
|
|
/* Tx power tracking switch,
|
||
|
|
* MP driver only */
|
||
|
|
FW_CMD_TXPWR_TRACK_ENABLE = 12,
|
||
|
|
/* Tx power tracking switch,
|
||
|
|
* MP driver only */
|
||
|
|
FW_CMD_TXPWR_TRACK_DISABLE = 13,
|
||
|
|
/* Tx power tracking with thermal
|
||
|
|
* indication, for Normal driver */
|
||
|
|
FW_CMD_TXPWR_TRACK_THERMAL = 14,
|
||
|
|
FW_CMD_PAUSE_DM_BY_SCAN = 15,
|
||
|
|
FW_CMD_RESUME_DM_BY_SCAN = 16,
|
||
|
|
FW_CMD_RA_REFRESH_N_COMB = 17,
|
||
|
|
FW_CMD_RA_REFRESH_BG_COMB = 18,
|
||
|
|
FW_CMD_ANTENNA_SW_ENABLE = 19,
|
||
|
|
FW_CMD_ANTENNA_SW_DISABLE = 20,
|
||
|
|
/* Tx Status report for CCX from FW */
|
||
|
|
FW_CMD_TX_FEEDBACK_CCX_ENABLE = 21,
|
||
|
|
/* Indifate firmware that driver
|
||
|
|
* enters LPS, For PS-Poll issue */
|
||
|
|
FW_CMD_LPS_ENTER = 22,
|
||
|
|
/* Indicate firmware that driver
|
||
|
|
* leave LPS*/
|
||
|
|
FW_CMD_LPS_LEAVE = 23,
|
||
|
|
/* Set DIG mode to signal strength */
|
||
|
|
FW_CMD_DIG_MODE_SS = 24,
|
||
|
|
/* Set DIG mode to false alarm. */
|
||
|
|
FW_CMD_DIG_MODE_FA = 25,
|
||
|
|
FW_CMD_ADD_A2_ENTRY = 26,
|
||
|
|
FW_CMD_CTRL_DM_BY_DRIVER = 27,
|
||
|
|
FW_CMD_CTRL_DM_BY_DRIVER_NEW = 28,
|
||
|
|
FW_CMD_PAPE_CONTROL = 29,
|
||
|
|
FW_CMD_IQK_ENABLE = 30,
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Driver info contain PHY status
|
||
|
|
* and other variabel size info
|
||
|
|
* PHY Status content as below
|
||
|
|
*/
|
||
|
|
struct rx_fwinfo {
|
||
|
|
/* DWORD 0 */
|
||
|
|
u8 gain_trsw[4];
|
||
|
|
/* DWORD 1 */
|
||
|
|
u8 pwdb_all;
|
||
|
|
u8 cfosho[4];
|
||
|
|
/* DWORD 2 */
|
||
|
|
u8 cfotail[4];
|
||
|
|
/* DWORD 3 */
|
||
|
|
s8 rxevm[2];
|
||
|
|
s8 rxsnr[4];
|
||
|
|
/* DWORD 4 */
|
||
|
|
u8 pdsnr[2];
|
||
|
|
/* DWORD 5 */
|
||
|
|
u8 csi_current[2];
|
||
|
|
u8 csi_target[2];
|
||
|
|
/* DWORD 6 */
|
||
|
|
u8 sigevm;
|
||
|
|
u8 max_ex_pwr;
|
||
|
|
u8 ex_intf_flag:1;
|
||
|
|
u8 sgi_en:1;
|
||
|
|
u8 rxsc:2;
|
||
|
|
u8 reserve:4;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct phy_sts_cck_8192s_t {
|
||
|
|
u8 adc_pwdb_x[4];
|
||
|
|
u8 sq_rpt;
|
||
|
|
u8 cck_agc_rpt;
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|