508 lines
13 KiB
C
508 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2009-2012 Realtek Corporation.*/
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#include "../wifi.h"
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#include "reg.h"
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#include "def.h"
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#include "phy.h"
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#include "rf.h"
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#include "dm.h"
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static void _rtl92s_get_powerbase(struct ieee80211_hw *hw, u8 *p_pwrlevel,
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u8 chnl, u32 *ofdmbase, u32 *mcsbase,
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u8 *p_final_pwridx)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
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u32 pwrbase0, pwrbase1;
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u8 legacy_pwrdiff = 0, ht20_pwrdiff = 0;
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u8 i, pwrlevel[4];
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for (i = 0; i < 2; i++)
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pwrlevel[i] = p_pwrlevel[i];
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/* We only care about the path A for legacy. */
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if (rtlefuse->eeprom_version < 2) {
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pwrbase0 = pwrlevel[0] + (rtlefuse->legacy_ht_txpowerdiff & 0xf);
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} else {
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legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff
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[RF90_PATH_A][chnl - 1];
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/* For legacy OFDM, tx pwr always > HT OFDM pwr.
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* We do not care Path B
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* legacy OFDM pwr diff. NO BB register
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* to notify HW. */
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pwrbase0 = pwrlevel[0] + legacy_pwrdiff;
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}
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pwrbase0 = (pwrbase0 << 24) | (pwrbase0 << 16) | (pwrbase0 << 8) |
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pwrbase0;
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*ofdmbase = pwrbase0;
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/* MCS rates */
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if (rtlefuse->eeprom_version >= 2) {
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/* Check HT20 to HT40 diff */
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if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
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for (i = 0; i < 2; i++) {
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/* rf-A, rf-B */
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/* HT 20<->40 pwr diff */
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ht20_pwrdiff = rtlefuse->txpwr_ht20diff
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[i][chnl - 1];
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if (ht20_pwrdiff < 8) /* 0~+7 */
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pwrlevel[i] += ht20_pwrdiff;
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else /* index8-15=-8~-1 */
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pwrlevel[i] -= (16 - ht20_pwrdiff);
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}
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}
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}
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/* use index of rf-A */
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pwrbase1 = pwrlevel[0];
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pwrbase1 = (pwrbase1 << 24) | (pwrbase1 << 16) | (pwrbase1 << 8) |
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pwrbase1;
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*mcsbase = pwrbase1;
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/* The following is for Antenna
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* diff from Ant-B to Ant-A */
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p_final_pwridx[0] = pwrlevel[0];
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p_final_pwridx[1] = pwrlevel[1];
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switch (rtlefuse->eeprom_regulatory) {
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case 3:
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/* The following is for calculation
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* of the power diff for Ant-B to Ant-A. */
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if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
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p_final_pwridx[0] += rtlefuse->pwrgroup_ht40
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[RF90_PATH_A][
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chnl - 1];
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p_final_pwridx[1] += rtlefuse->pwrgroup_ht40
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[RF90_PATH_B][
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chnl - 1];
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} else {
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p_final_pwridx[0] += rtlefuse->pwrgroup_ht20
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[RF90_PATH_A][
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chnl - 1];
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p_final_pwridx[1] += rtlefuse->pwrgroup_ht20
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[RF90_PATH_B][
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chnl - 1];
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}
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break;
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default:
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break;
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}
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if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
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rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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"40MHz finalpwr_idx (A / B) = 0x%x / 0x%x\n",
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p_final_pwridx[0], p_final_pwridx[1]);
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} else {
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rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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"20MHz finalpwr_idx (A / B) = 0x%x / 0x%x\n",
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p_final_pwridx[0], p_final_pwridx[1]);
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}
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}
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static void _rtl92s_set_antennadiff(struct ieee80211_hw *hw,
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u8 *p_final_pwridx)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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s8 ant_pwr_diff = 0;
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u32 u4reg_val = 0;
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if (rtlphy->rf_type == RF_2T2R) {
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ant_pwr_diff = p_final_pwridx[1] - p_final_pwridx[0];
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/* range is from 7~-8,
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* index = 0x0~0xf */
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if (ant_pwr_diff > 7)
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ant_pwr_diff = 7;
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if (ant_pwr_diff < -8)
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ant_pwr_diff = -8;
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rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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"Antenna Diff from RF-B to RF-A = %d (0x%x)\n",
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ant_pwr_diff, ant_pwr_diff & 0xf);
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ant_pwr_diff &= 0xf;
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}
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/* Antenna TX power difference */
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rtlefuse->antenna_txpwdiff[2] = 0;/* RF-D, don't care */
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rtlefuse->antenna_txpwdiff[1] = 0;/* RF-C, don't care */
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rtlefuse->antenna_txpwdiff[0] = (u8)(ant_pwr_diff); /* RF-B */
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u4reg_val = rtlefuse->antenna_txpwdiff[2] << 8 |
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rtlefuse->antenna_txpwdiff[1] << 4 |
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rtlefuse->antenna_txpwdiff[0];
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rtl_set_bbreg(hw, RFPGA0_TXGAINSTAGE, (BXBTXAGC | BXCTXAGC | BXDTXAGC),
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u4reg_val);
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rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Write BCD-Diff(0x%x) = 0x%x\n",
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RFPGA0_TXGAINSTAGE, u4reg_val);
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}
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static void _rtl92s_get_txpower_writeval_byregulatory(struct ieee80211_hw *hw,
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u8 chnl, u8 index,
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u32 pwrbase0,
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u32 pwrbase1,
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u32 *p_outwrite_val)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
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u8 i, chnlgroup, pwrdiff_limit[4];
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u32 writeval, customer_limit;
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/* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
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switch (rtlefuse->eeprom_regulatory) {
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case 0:
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/* Realtek better performance increase power diff
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* defined by Realtek for large power */
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chnlgroup = 0;
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writeval = rtlphy->mcs_offset[chnlgroup][index] +
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((index < 2) ? pwrbase0 : pwrbase1);
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rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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"RTK better performance, writeval = 0x%x\n", writeval);
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break;
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case 1:
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/* Realtek regulatory increase power diff defined
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* by Realtek for regulatory */
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if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
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writeval = ((index < 2) ? pwrbase0 : pwrbase1);
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rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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"Realtek regulatory, 40MHz, writeval = 0x%x\n",
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writeval);
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} else {
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chnlgroup = 0;
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if (rtlphy->pwrgroup_cnt >= 3) {
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if (chnl <= 3)
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chnlgroup = 0;
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else if (chnl >= 4 && chnl <= 8)
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chnlgroup = 1;
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else if (chnl > 8)
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chnlgroup = 2;
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if (rtlphy->pwrgroup_cnt == 4)
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chnlgroup++;
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}
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writeval = rtlphy->mcs_offset[chnlgroup][index]
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+ ((index < 2) ?
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pwrbase0 : pwrbase1);
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rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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"Realtek regulatory, 20MHz, writeval = 0x%x\n",
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writeval);
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}
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break;
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case 2:
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/* Better regulatory don't increase any power diff */
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writeval = ((index < 2) ? pwrbase0 : pwrbase1);
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rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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"Better regulatory, writeval = 0x%x\n", writeval);
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break;
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case 3:
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/* Customer defined power diff. increase power diff
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defined by customer. */
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chnlgroup = 0;
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if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
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rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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"customer's limit, 40MHz = 0x%x\n",
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rtlefuse->pwrgroup_ht40
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[RF90_PATH_A][chnl - 1]);
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} else {
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rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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"customer's limit, 20MHz = 0x%x\n",
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rtlefuse->pwrgroup_ht20
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[RF90_PATH_A][chnl - 1]);
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}
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for (i = 0; i < 4; i++) {
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pwrdiff_limit[i] = (u8)((rtlphy->mcs_offset
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[chnlgroup][index] & (0x7f << (i * 8)))
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>> (i * 8));
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if (rtlphy->current_chan_bw ==
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HT_CHANNEL_WIDTH_20_40) {
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if (pwrdiff_limit[i] >
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rtlefuse->pwrgroup_ht40
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[RF90_PATH_A][chnl - 1]) {
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pwrdiff_limit[i] =
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rtlefuse->pwrgroup_ht40
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[RF90_PATH_A][chnl - 1];
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}
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} else {
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if (pwrdiff_limit[i] >
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rtlefuse->pwrgroup_ht20
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[RF90_PATH_A][chnl - 1]) {
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pwrdiff_limit[i] =
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rtlefuse->pwrgroup_ht20
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[RF90_PATH_A][chnl - 1];
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}
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}
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}
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customer_limit = (pwrdiff_limit[3] << 24) |
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(pwrdiff_limit[2] << 16) |
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(pwrdiff_limit[1] << 8) |
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(pwrdiff_limit[0]);
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rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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"Customer's limit = 0x%x\n", customer_limit);
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writeval = customer_limit + ((index < 2) ?
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pwrbase0 : pwrbase1);
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rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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"Customer, writeval = 0x%x\n", writeval);
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break;
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default:
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chnlgroup = 0;
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writeval = rtlphy->mcs_offset[chnlgroup][index] +
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((index < 2) ? pwrbase0 : pwrbase1);
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rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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"RTK better performance, writeval = 0x%x\n", writeval);
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break;
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}
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if (rtlpriv->dm.dynamic_txhighpower_lvl == TX_HIGH_PWR_LEVEL_LEVEL1)
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writeval = 0x10101010;
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else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
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TX_HIGH_PWR_LEVEL_LEVEL2)
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writeval = 0x0;
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*p_outwrite_val = writeval;
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}
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static void _rtl92s_write_ofdm_powerreg(struct ieee80211_hw *hw,
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u8 index, u32 val)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
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u16 regoffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
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u8 i, rfa_pwr[4];
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u8 rfa_lower_bound = 0, rfa_upper_bound = 0, rf_pwr_diff = 0;
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u32 writeval = val;
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/* If path A and Path B coexist, we must limit Path A tx power.
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* Protect Path B pwr over or under flow. We need to calculate
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* upper and lower bound of path A tx power. */
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if (rtlphy->rf_type == RF_2T2R) {
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rf_pwr_diff = rtlefuse->antenna_txpwdiff[0];
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/* Diff=-8~-1 */
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if (rf_pwr_diff >= 8) {
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/* Prevent underflow!! */
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rfa_lower_bound = 0x10 - rf_pwr_diff;
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/* if (rf_pwr_diff >= 0) Diff = 0-7 */
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} else {
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rfa_upper_bound = RF6052_MAX_TX_PWR - rf_pwr_diff;
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}
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}
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for (i = 0; i < 4; i++) {
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rfa_pwr[i] = (u8)((writeval & (0x7f << (i * 8))) >> (i * 8));
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if (rfa_pwr[i] > RF6052_MAX_TX_PWR)
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rfa_pwr[i] = RF6052_MAX_TX_PWR;
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/* If path A and Path B coexist, we must limit Path A tx power.
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* Protect Path B pwr over or under flow. We need to calculate
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* upper and lower bound of path A tx power. */
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if (rtlphy->rf_type == RF_2T2R) {
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/* Diff=-8~-1 */
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if (rf_pwr_diff >= 8) {
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/* Prevent underflow!! */
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if (rfa_pwr[i] < rfa_lower_bound)
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rfa_pwr[i] = rfa_lower_bound;
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/* Diff = 0-7 */
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} else if (rf_pwr_diff >= 1) {
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/* Prevent overflow */
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if (rfa_pwr[i] > rfa_upper_bound)
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rfa_pwr[i] = rfa_upper_bound;
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}
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}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
writeval = (rfa_pwr[3] << 24) | (rfa_pwr[2] << 16) | (rfa_pwr[1] << 8) |
|
||
|
|
rfa_pwr[0];
|
||
|
|
|
||
|
|
rtl_set_bbreg(hw, regoffset[index], 0x7f7f7f7f, writeval);
|
||
|
|
}
|
||
|
|
|
||
|
|
void rtl92s_phy_rf6052_set_ofdmtxpower(struct ieee80211_hw *hw,
|
||
|
|
u8 *p_pwrlevel, u8 chnl)
|
||
|
|
{
|
||
|
|
u32 writeval, pwrbase0, pwrbase1;
|
||
|
|
u8 index = 0;
|
||
|
|
u8 finalpwr_idx[4];
|
||
|
|
|
||
|
|
_rtl92s_get_powerbase(hw, p_pwrlevel, chnl, &pwrbase0, &pwrbase1,
|
||
|
|
&finalpwr_idx[0]);
|
||
|
|
_rtl92s_set_antennadiff(hw, &finalpwr_idx[0]);
|
||
|
|
|
||
|
|
for (index = 0; index < 6; index++) {
|
||
|
|
_rtl92s_get_txpower_writeval_byregulatory(hw, chnl, index,
|
||
|
|
pwrbase0, pwrbase1, &writeval);
|
||
|
|
|
||
|
|
_rtl92s_write_ofdm_powerreg(hw, index, writeval);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void rtl92s_phy_rf6052_set_ccktxpower(struct ieee80211_hw *hw, u8 pwrlevel)
|
||
|
|
{
|
||
|
|
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||
|
|
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
|
||
|
|
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
|
||
|
|
u32 txagc = 0;
|
||
|
|
bool dont_inc_cck_or_turboscanoff = false;
|
||
|
|
|
||
|
|
if (((rtlefuse->eeprom_version >= 2) &&
|
||
|
|
(rtlefuse->txpwr_safetyflag == 1)) ||
|
||
|
|
((rtlefuse->eeprom_version >= 2) &&
|
||
|
|
(rtlefuse->eeprom_regulatory != 0)))
|
||
|
|
dont_inc_cck_or_turboscanoff = true;
|
||
|
|
|
||
|
|
if (mac->act_scanning) {
|
||
|
|
txagc = 0x3f;
|
||
|
|
if (dont_inc_cck_or_turboscanoff)
|
||
|
|
txagc = pwrlevel;
|
||
|
|
} else {
|
||
|
|
txagc = pwrlevel;
|
||
|
|
|
||
|
|
if (rtlpriv->dm.dynamic_txhighpower_lvl ==
|
||
|
|
TX_HIGH_PWR_LEVEL_LEVEL1)
|
||
|
|
txagc = 0x10;
|
||
|
|
else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
|
||
|
|
TX_HIGH_PWR_LEVEL_LEVEL2)
|
||
|
|
txagc = 0x0;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (txagc > RF6052_MAX_TX_PWR)
|
||
|
|
txagc = RF6052_MAX_TX_PWR;
|
||
|
|
|
||
|
|
rtl_set_bbreg(hw, RTXAGC_CCK_MCS32, BTX_AGCRATECCK, txagc);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
bool rtl92s_phy_rf6052_config(struct ieee80211_hw *hw)
|
||
|
|
{
|
||
|
|
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||
|
|
struct rtl_phy *rtlphy = &(rtlpriv->phy);
|
||
|
|
u32 u4reg_val = 0;
|
||
|
|
u8 rfpath;
|
||
|
|
bool rtstatus = true;
|
||
|
|
struct bb_reg_def *pphyreg;
|
||
|
|
|
||
|
|
/* Initialize RF */
|
||
|
|
for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
|
||
|
|
|
||
|
|
pphyreg = &rtlphy->phyreg_def[rfpath];
|
||
|
|
|
||
|
|
/* Store original RFENV control type */
|
||
|
|
switch (rfpath) {
|
||
|
|
case RF90_PATH_A:
|
||
|
|
case RF90_PATH_C:
|
||
|
|
u4reg_val = rtl92s_phy_query_bb_reg(hw,
|
||
|
|
pphyreg->rfintfs,
|
||
|
|
BRFSI_RFENV);
|
||
|
|
break;
|
||
|
|
case RF90_PATH_B:
|
||
|
|
case RF90_PATH_D:
|
||
|
|
u4reg_val = rtl92s_phy_query_bb_reg(hw,
|
||
|
|
pphyreg->rfintfs,
|
||
|
|
BRFSI_RFENV << 16);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Set RF_ENV enable */
|
||
|
|
rtl92s_phy_set_bb_reg(hw, pphyreg->rfintfe,
|
||
|
|
BRFSI_RFENV << 16, 0x1);
|
||
|
|
|
||
|
|
/* Set RF_ENV output high */
|
||
|
|
rtl92s_phy_set_bb_reg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
|
||
|
|
|
||
|
|
/* Set bit number of Address and Data for RF register */
|
||
|
|
rtl92s_phy_set_bb_reg(hw, pphyreg->rfhssi_para2,
|
||
|
|
B3WIRE_ADDRESSLENGTH, 0x0);
|
||
|
|
rtl92s_phy_set_bb_reg(hw, pphyreg->rfhssi_para2,
|
||
|
|
B3WIRE_DATALENGTH, 0x0);
|
||
|
|
|
||
|
|
/* Initialize RF fom connfiguration file */
|
||
|
|
switch (rfpath) {
|
||
|
|
case RF90_PATH_A:
|
||
|
|
rtstatus = rtl92s_phy_config_rf(hw,
|
||
|
|
(enum radio_path)rfpath);
|
||
|
|
break;
|
||
|
|
case RF90_PATH_B:
|
||
|
|
rtstatus = rtl92s_phy_config_rf(hw,
|
||
|
|
(enum radio_path)rfpath);
|
||
|
|
break;
|
||
|
|
case RF90_PATH_C:
|
||
|
|
break;
|
||
|
|
case RF90_PATH_D:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Restore RFENV control type */
|
||
|
|
switch (rfpath) {
|
||
|
|
case RF90_PATH_A:
|
||
|
|
case RF90_PATH_C:
|
||
|
|
rtl92s_phy_set_bb_reg(hw, pphyreg->rfintfs, BRFSI_RFENV,
|
||
|
|
u4reg_val);
|
||
|
|
break;
|
||
|
|
case RF90_PATH_B:
|
||
|
|
case RF90_PATH_D:
|
||
|
|
rtl92s_phy_set_bb_reg(hw, pphyreg->rfintfs,
|
||
|
|
BRFSI_RFENV << 16,
|
||
|
|
u4reg_val);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!rtstatus) {
|
||
|
|
pr_err("Radio[%d] Fail!!\n", rfpath);
|
||
|
|
goto fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
return rtstatus;
|
||
|
|
|
||
|
|
fail:
|
||
|
|
return rtstatus;
|
||
|
|
}
|
||
|
|
|
||
|
|
void rtl92s_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
|
||
|
|
{
|
||
|
|
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||
|
|
struct rtl_phy *rtlphy = &(rtlpriv->phy);
|
||
|
|
|
||
|
|
switch (bandwidth) {
|
||
|
|
case HT_CHANNEL_WIDTH_20:
|
||
|
|
rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
|
||
|
|
0xfffff3ff) | 0x0400);
|
||
|
|
rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
|
||
|
|
rtlphy->rfreg_chnlval[0]);
|
||
|
|
break;
|
||
|
|
case HT_CHANNEL_WIDTH_20_40:
|
||
|
|
rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
|
||
|
|
0xfffff3ff));
|
||
|
|
rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
|
||
|
|
rtlphy->rfreg_chnlval[0]);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
pr_err("unknown bandwidth: %#X\n", bandwidth);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|