88 lines
1.6 KiB
C
88 lines
1.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2019-2022 Realtek Corporation
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*/
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#ifndef __RTW89_8852C_H__
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#define __RTW89_8852C_H__
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#include "core.h"
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#define RF_PATH_NUM_8852C 2
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#define BB_PATH_NUM_8852C 2
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struct rtw8852c_u_efuse {
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u8 rsvd[0x38];
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u8 mac_addr[ETH_ALEN];
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};
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struct rtw8852c_e_efuse {
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u8 mac_addr[ETH_ALEN];
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};
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struct rtw8852c_tssi_offset {
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u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
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u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
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u8 rsvd[7];
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u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
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} __packed;
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struct rtw8852c_efuse {
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u8 rsvd[0x210];
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struct rtw8852c_tssi_offset path_a_tssi;
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u8 rsvd1[10];
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struct rtw8852c_tssi_offset path_b_tssi;
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u8 rsvd2[94];
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u8 channel_plan;
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u8 xtal_k;
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u8 rsvd3;
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u8 iqk_lck;
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u8 rsvd4[5];
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u8 reg_setting:2;
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u8 tx_diversity:1;
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u8 rx_diversity:2;
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u8 ac_mode:1;
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u8 module_type:2;
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u8 rsvd5;
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u8 shared_ant:1;
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u8 coex_type:3;
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u8 ant_iso:1;
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u8 radio_on_off:1;
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u8 rsvd6:2;
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u8 eeprom_version;
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u8 customer_id;
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u8 tx_bb_swing_2g;
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u8 tx_bb_swing_5g;
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u8 tx_cali_pwr_trk_mode;
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u8 trx_path_selection;
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u8 rfe_type;
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u8 country_code[2];
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u8 rsvd7[3];
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u8 path_a_therm;
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u8 path_b_therm;
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u8 rsvd8[2];
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u8 rx_gain_2g_ofdm;
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u8 rsvd9;
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u8 rx_gain_2g_cck;
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u8 rsvd10;
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u8 rx_gain_5g_low;
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u8 rsvd11;
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u8 rx_gain_5g_mid;
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u8 rsvd12;
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u8 rx_gain_5g_high;
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u8 rsvd13[35];
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u8 bw40_1s_tssi_6g_a[TSSI_MCS_6G_CH_GROUP_NUM];
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u8 rsvd14[10];
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u8 bw40_1s_tssi_6g_b[TSSI_MCS_6G_CH_GROUP_NUM];
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u8 rsvd15[110];
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u8 channel_plan_6g;
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u8 rsvd16[71];
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union {
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struct rtw8852c_u_efuse u;
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struct rtw8852c_e_efuse e;
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};
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} __packed;
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extern const struct rtw89_chip_info rtw8852c_chip_info;
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#endif
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